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intermittent booting please help

Can someone please help me Im really stuck

I built a ADSP-21261 custom board, the system seems to have successfully booted via from M2516 SPI flash (in master mode), however im finding a problem with intermittent booting,where the board doesn't successfully boot the system first time during power up, most of the time I have to power cycle the board quite a few times to get the board to boot correctly.

Note: the program is very simple it just toggles Flag1 so no PLL software setup was used and the clock config is set to 3:1, this is obviously used to test the the boot sequence.

I've read all most of the SHARCEE engineering docs referenced on the forum, so far I haven't found a solution or cause to why this is happening the docs does have alot of useful information which I have taken into consideration, but this problem seems unique.

This experiences seems similar to post https://ez.analog.com/message/138620#138620 however im using a ADSP-21261

Here is my setup

1) I'm using CCES 1.0.3

2) Here is my cldp command (which seems to work)

cldp -proc ADSP-21262 -emu "ICE-100" -driver "C:\Users\admin\CrossCore Embedded Studio\examples\21262_ezkit_lite_1.0.0\M25P16_Flasher\Debug\M2516_Flasher.dxe"   -cmd prog -erase all -format hex -file "C:\Users\admin\CrossCore Embedded Studio\examples\21262_ezkit_lite_1.0.0\Core_Timer\Debug\Core_Timer.ldr"  -cmd compare  -format hex  -offset 0  -file "C:\Users\admin\CrossCore Embedded Studio\examples\21262_ezkit_lite_1.0.0\Core_Timer\Debug\Core_Timer.ldr"

3) See attachment for my SHARC loader settings.

4) I'm using the default kernel, I'm using the following CrossCore Embedded Studio 1.0.3\SHARC\ldr\26x_spi.dxe

5) Find some attachments illustrating the problem

attachments.zip
  • A few things to look into:

    power up timing: there is a minimum delay required between the FLASH Vcc going into regulation and S# going low.

    This seems unlikely to be a problem in your case unless your supply is really flaky.

    There is also the power up timing of the processor itself, the requirements of which are described in the hardware reference manual.

    signal integrity: make sure that the FLASH does not see ringing or non-monotonic edges on its clock line. Does the layout follow transmission line rules? Are your supplies stable and well decoupled?

    When you zoom in on the first word, does the command always come out correct?

    What does the reset line to the SHARC look like and how are you generating it? What about the clock?

    Anything hanging off the JTAG pins?

    It looks like on a few attempts the processor does not load the 256 32 it words. Since this is a hardwired functionality the part either gets reset again during the boot or hangs for some other reasons.

    Klaus

  • Hi Klaus!, firstly thanks for the help, really appreciate it.

    Power up timing: there is a minimum delay required between the FLASH Vcc going into regulation and S# going low.

    see attachment here the flash section of my board, its a replica of the ez-kit flash section found in most of the board.

    This seems unlikely to be a problem in your case unless your supply is really flaky.

    There is also the power up timing of the processor itself, the requirements of which are described in the hardware reference manual.

    I use a DP832 Rigol laboratory power supply,and my supply uses local low drop out regulators power up seems very normal in terms of ramp up time and noise measurements. see attachments.

    signal integrity: make sure that the FLASH does not see ringing or non-monotonic edges on its clock line. Does the layout follow transmission line rules? Are your supplies stable and well decoupled

       I probed the clock line what I noticed is sometimes I don't always receive a stable clock, I have simple rules like keeping the clock line short and psu lines 1.2v and 3.3v decoupled seen on the diagram

    When you zoom in on the first word, does the command always come out correct?

    What does the reset line to the SHARC look like and how are you generating it? What about the clock?

    Anything hanging off the JTAG pins?

     

    It looks like on a few attempts the processor does not load the 256 32 it words. Since this is a hardwired functionality the part either gets reset again during the boot or hangs for some other reasons.

    I found whilst responding there seems to be issues with the SPI clock no generating at all during boot OR sometimes the clock is just unstable all the time and explains why no stable read request commands are not showing

    It looks it might be a clock stability issue, I will report back later my findings.. if anyone can throw a few tips I would appreciate it

    attachments.zip
  • I'm not sure if this is an issue, I doubt it is see attachment.

    The ADSP-21262 (200Mhz) shows a example external crystal of 12.5Mhz with PLL multiplier of 16:1 thats 12.5 x 16 = 200MHz during boot,

    However, Im using a ADSP-21261 (150Mhz) with a 25MHz crystal with a PLL multiplier of 3:1 thats 25 * 3 = 75Mhz during boot.

    My question is will the lowered clock rate of 75MHz cause an issue during SPI boot?Can this be responsible for the intermittent booting I'm experiencing?

  • Greetings AlClark thanks for the help.

    Honestly, I don't have that 1-meg resistor fitted,  I'm going to check the effects this resistor has on the clock and document my findings. I didn't know the ADSP-2126x PLL was highly susceptible to noise if I did I would have taken extra care during layout (note this was my first board I made).. but this is just a educational research effort. 

    Appreciate the help friend.

  • Do you have a resistor across the xtal? This would be large maybe 1-10M Ohm? 

    I seem to recall that the PLL was also a little noise susceptible with the 2126x. Check the PLL layout and filtering.

    Running at 75MHz will not effect flash boot, except for speed.

    Al Clark

    www.danvillesignal.com

  • Hi,

    PLL is the heart of the SHARC processors, and requires robust hardware and software handling.

    If you face problems based on PLL changes the following can be checked out in the system:

    1. Is the power-up specification met according to the data sheet (valid core and IO voltage, input clock, reset signal)?
    2. Are the CLK_CFG pins static (may change only during reset)?

    Can you also monitor CLOCK at the time of booting?

    The ADSP-2126x has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement.

    Analog supply pin (AVDD) powers the ADSP-2126x’s internal clock generator PLL. To produce a stable clock, it is recommended that PCB designs use an external filter circuit for the AVDD pin. Can you make sure that the analog power filter circuit is same as mentioned in the datasheet on page 7.

    This should give us some idea.

    Please let us know if you have any further queries.

    Regards,

    Harshit

  • Klaus, AlClark and Harshit Thank You very much

    The problem was the missing 22-pf xtal loading caps, as well as the missing 1-meg resistor (this was mentioned in the datasheet and I overlooked this) after these components was fitted the system booted fine on every power cycle.


    The SPI clock showed signs of a stability during boot. 


    I really learned a hard lesson which I shall never forget. I think im ready to design a board with a newer generation processor.