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how can i write/read two bytes to the TWI interface using ADSP21489?

Hi  everyone

                I ues the TWI interface of SHARC reading the tempereture sensor.Now, i use the example of the Power_On_Self_Test  and  i can write/read one byte data to the TWI interface. But i can not  write/read two bytes to the TWI interface.

              MY slave is the tmp112,i read the datasheet, the time diagram is below.

   

//THE CODE        

void I2C_Master_Write (unsigned int data, unsigned int address)
{

/* setup flag */
g_write_pend = 1;

/* write address to the 8-bit TX fifo */
*pTXTWI8 = address;

/* enable master transfer complete and TX FIFO service interrupts */
*pTWIIMASK = TWIMCOM | TWITXINT;

/* setup for 2 data bytes, master enable, master TX */
*pTWIMCTL = TWIDCNT2 | TWIMEN;

/* wait for data */
while ( g_buff_empty != 1 )
{
;
}

/* write data to the 8-bit TX fifo */
*pTXTWI8 = data;

/* reset flag */
g_buff_empty = 1;

/* wait for write to complete */
while( g_write_pend == 1 )
{
;
}

/* write data to the 8-bit TX fifo */
*pTXTWI8 = data;

/* reset flag */
g_buff_empty = 1;

/* wait for write to complete */
while( g_write_pend == 1 )
{
;
}

}


int Read_TWI_Register(int address)
{
int temp; /* temporary int */


/* setup flags, to read we do both write and read */
g_write_pend = 1;
g_read_pend = 1;

/* write address to the 8-bit TX fifo */
*pTXTWI8 = address;

/* enable master transfer complete interrupt */
*pTWIIMASK = TWIMCOM;

/* setup for 1 data byte, master enable, master TX */
*pTWIMCTL = TWIDCNT1 | TWIMEN;

/* wait for write to complete */
while( g_write_pend == 1 )
{
;
}

/* setup for 1 data byte, master enable, master RX */
*pTWIMCTL = TWIDCNT1 | TWIMEN | TWIMDIR;

/* wait for read to complete */
while( g_read_pend == 1 )
{
;
}

/* read data from the 8-bit RX fifo */
temp = *pRXTWI8;

return temp;
}

catching  the wave from the OSC

the write

the read

hope someone can give me some advice,thanks.

                                                                              jack

attachments.zip
Parents
  • The TWI FIFO buffer is configured as a 1-byte-wide, 2-deep transmit FIFO buffer and a 1-byte-wide, 2-deep receive FIFO buffer. The TWI 16-bit FIFO transmit register (TXTWI16) and TWI 16-bit FIFO receive register (RXTWI16) holds a 16-bit data value written into / read from the FIFO buffer respectively. Although peripheral bus reads are 32 bits, a read access to the TXTWI16/RXTWI16 register can only access two receive data bytes from the FIFO buffer. To reduce interrupt output rates and peripheral bus access times, a double-byte receive data access can be performed. Two data bytes can be read, effectively emptying the receive FIFO buffer with a single access.

    You can program the  the TWIFIFOCTL register to indicate if transmit (or receive) FIFO buffer interrupts should occur with each byte transmitted (received) or with each 2 bytes transmitted (received). So could you please check with 16-bit standard mode transfer and see if it meets your requirement. 

Reply
  • The TWI FIFO buffer is configured as a 1-byte-wide, 2-deep transmit FIFO buffer and a 1-byte-wide, 2-deep receive FIFO buffer. The TWI 16-bit FIFO transmit register (TXTWI16) and TWI 16-bit FIFO receive register (RXTWI16) holds a 16-bit data value written into / read from the FIFO buffer respectively. Although peripheral bus reads are 32 bits, a read access to the TXTWI16/RXTWI16 register can only access two receive data bytes from the FIFO buffer. To reduce interrupt output rates and peripheral bus access times, a double-byte receive data access can be performed. Two data bytes can be read, effectively emptying the receive FIFO buffer with a single access.

    You can program the  the TWIFIFOCTL register to indicate if transmit (or receive) FIFO buffer interrupts should occur with each byte transmitted (received) or with each 2 bytes transmitted (received). So could you please check with 16-bit standard mode transfer and see if it meets your requirement. 

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