Maybe someone could help me with boot kernel information I miss.
I try to fix a device where the ADSP-21266SKSTZ-1B. The processor was getting hot, it was impossible to connect with HP-USB debug probe so first of all I've replaced it.
After such action the IC doesn't get hot anymore, debug connection seems possible.
It looks lile the processor loads 256 words of boot kernel, because after connecting the debug probe end generating reset the core stops at address 80005 (which seems to be the boot kernel entry point).
After starting the code, it goes to a loop, and seem to stuck at following instructions
[0008001D] r1=pass r1;
[0008001E] if eq jump (pc, 0xffffffff);
I can tell that the boot kernel was read from flash correctly via parallel port, because the first 256 words at address 0x00080000 (internal SRAM) match the words at address 0x01000000 (external Flash).
The processor has the BOOT_CFG lines configured for Parallel Port Boot via EPROM boot.
Looks like the communication via parallel bus works fine (boot kernel in Flash/ 1M x 8bit accessible, external SRAM/ 128k x *bit at 0x01400000 also seems to work fine / is writable, preserves data).
I've attached the boot kernel dump (from RAM) as disassembly.
I suspect that the code for mentioned loop waits for the SPI or Parallel Port interrupt, but I'm not sure what rationale for that would it have at boot stage here.
At the stage when execution stucks at the mentioned loop, in the LIRPTL following flags are set:
Is that possile that the SHARC processor waits for the another processor (which it's interconnected with SPI interface) to be given boot info for regions to be loaded into the internal RAM?
That assumption appeared when I took a look at the original 26x_prom.asm boot kernel assembly.
I'll add any more information you need (about the hardware and content of the registers of processor when debugging the code) if necessary.
Any help would be greatly appreciated.