I was searching through the discussions here but there was not the answer I was looking for.
I'm using the ADSP-21489 in my design which is sending and receiving data on all SPORTs (A and B).
Each SPORT channel is running with DMA chaining to/from PING/PONG buffers.
The data format is 32Bit I2S with 2 or 8 channels with 96kHz samplerate, all clocks are supplied external from an FPGA.
Obviously the data change of the 8-channel I2S lines occurs earlier than on 2-channel I2S.
Also the interrupts from transmitters are coming earlier (relative to L/R clock) than receivers.
I need to trigger an audio processing interrupt every sample where I copy the data to/from PING/PONG buffers for further processing. At the moment I'm using the interrupt from the lowest priority 2-channel receiver SPORT DMA channel for starting processing. E.g. SP0=RX2, SP1=RX2, SP2=RX8, SP3=TX8, SP4=TX2, SP5=RX8, SP6=TX8 -> using SP0 IRQ.
Is there a "good practice" guideline or application note for such a configuration?
Any recommendations on which SPORT channel should be used for what data (priority levels!!), which SPORT interrupt to use for synchronisation, etc..? Shoud I put 8-channel lines to higher priority SPORTs than 2-channel lines?
How to start such a configuration safely in sync?