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SPORT synchronisation


I was searching through the discussions here but there was not the answer I was looking for.

I'm using the ADSP-21489 in my design which is sending and receiving data on all SPORTs (A and B).

Each SPORT channel is running with DMA chaining to/from PING/PONG buffers.

The data format is 32Bit I2S with 2 or 8 channels with 96kHz samplerate, all clocks are supplied external from an FPGA.

Obviously the data change of the 8-channel I2S lines occurs earlier than on 2-channel I2S.

Also the interrupts from transmitters are coming earlier (relative to L/R clock) than receivers.

I need to trigger an audio processing interrupt every sample where I copy the data to/from PING/PONG buffers for further processing. At the moment I'm using the interrupt from the lowest priority 2-channel receiver SPORT DMA channel for starting processing. E.g. SP0=RX2, SP1=RX2, SP2=RX8, SP3=TX8, SP4=TX2, SP5=RX8, SP6=TX8 -> using SP0 IRQ.

Is there a "good practice" guideline or application note for such a configuration?

Any recommendations on which SPORT channel should be used for what data (priority levels!!), which SPORT interrupt to use for synchronisation, etc..? Shoud I put 8-channel lines to higher priority SPORTs than 2-channel lines?

How to start such a configuration safely in sync?



  • Please pet me know if you have a better definition of what “2 or 8-channel I2S” means? Are you talking about SPORT configured in multichannel mode (rather you mentioned as I2S)?

    The ADSP-21489 processors have eight independent, synchronous serial ports (SPORTs) has two bidirectional channels (A and B) per serial port, configurable as either transmitters or receivers. Each SPORT has its own set of control registers and data buffers. 

    Could you please elaborate what kind of SPORT synchronization are you looking for here?

  • Hello Jithul,

    of course the 8-channel I2S is multichannel mode with a 1 BCLK delay of the data (so I2S like).

    With synchronisation I mean which SPORT DMA interrupt to use best to start audio processing on the data i.e. which DMA IRQ is the "latest" of them so that all data words from the preceeding sample have been stored or received by all SPORT DMAs. I saw TX IRQs come earlier than RX, 8-channel of course also (because 8-channel BCLK is faster than 2-channel).

    Also regarding start of the SPORT interfaces and DMAs I saw that when waiting for the inactive LRCLK level as proposed and I start the SPORTs in that phase the TX DMAs already start working while RX DMAs are starting with the active LRCLK...



  • Hi Christian,

    have you considered the ETDINTEN bit in SPCTLNx?

    ETDINTEN External Transfer Done Interrupt. If set, interrupt occurs only after
    the last bit of last word in the DMA is shifted out. If cleared, interrupt occurs when the DMA counter expires.




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