Post Go back to editing

ADSP-21477 how routing SPORTs in SRU matrix

Hi all,
I have to develope a project using the ADSP-21477 and I'm checking the DSP's pinout, in my application I have to connect all the SPORT to the FPGA.
I read the documents: "ADSP-214xx SHARCRegistered Processor Hardware Reference" and "Configuring the Signal Routing Unit of ADSP-2126x SHARCRegistered DSPs (EE-232)" to understand how pin routing works in SRU matrix.

Datasheet tells that the SPORT signal are routed on DAI pins (as shown by Figure 1 of datasheet) but if I have 20 DAI pins how I can map 8 SPORT interface (4x8=32 pins)?

Thanks.

Parents
  • Hello,

    As you are stated correctly there are only 20 DAI pins and all the SPORT signals can be routed only through DAI pins. In case, if you application use same CLK and FS for all the 8 SPORTs, the Master CLK and FS can be routed to 2 DAI pins and these pins can be used to provide CLK and FS to all the SPORTs using SRU. 

    For instance, if the master clock and FS arrives at DAI_PB01 and DAI_P02 respectively, it can be routed internally to other SPORT as given below.

    // Tie the pin buffer input LOW.
    SRU(LOW,DAI_PB01_I);

    SRU(LOW,DAI_PB02_I);

    // Tie the pin buffer enable input LOW
    SRU(LOW,PBEN01_I);

    SRU(LOW,PBEN02_I);

    // Clock in from DAI01 connects to different SPORT_CLK input 
    SRU(DAI_PB01_O, SPORT0_CLK_I);

    SRU(DAI_PB01_O, SPORT1_CLK_I);

     

    // FS from DAI02 connects to different SPORT_FS input 

    SRU(DAI_PB02_O, SPORT0_FS_I);

    SRU(DAI_PB02_O, SPORT1_FS_I);  

     

    In other case if you want to connect internally generated SPORT clock or FS to other SPORTs, you can use as following
    SRU (SPORT0_CLK_O , SPORT1_CLK_I);

    SRU (SPORT0_FS_O, SPORT1_FS_I);

     

    Best Regards,

    Jithul

Reply
  • Hello,

    As you are stated correctly there are only 20 DAI pins and all the SPORT signals can be routed only through DAI pins. In case, if you application use same CLK and FS for all the 8 SPORTs, the Master CLK and FS can be routed to 2 DAI pins and these pins can be used to provide CLK and FS to all the SPORTs using SRU. 

    For instance, if the master clock and FS arrives at DAI_PB01 and DAI_P02 respectively, it can be routed internally to other SPORT as given below.

    // Tie the pin buffer input LOW.
    SRU(LOW,DAI_PB01_I);

    SRU(LOW,DAI_PB02_I);

    // Tie the pin buffer enable input LOW
    SRU(LOW,PBEN01_I);

    SRU(LOW,PBEN02_I);

    // Clock in from DAI01 connects to different SPORT_CLK input 
    SRU(DAI_PB01_O, SPORT0_CLK_I);

    SRU(DAI_PB01_O, SPORT1_CLK_I);

     

    // FS from DAI02 connects to different SPORT_FS input 

    SRU(DAI_PB02_O, SPORT0_FS_I);

    SRU(DAI_PB02_O, SPORT1_FS_I);  

     

    In other case if you want to connect internally generated SPORT clock or FS to other SPORTs, you can use as following
    SRU (SPORT0_CLK_O , SPORT1_CLK_I);

    SRU (SPORT0_FS_O, SPORT1_FS_I);

     

    Best Regards,

    Jithul

Children
No Data