Porting software  from ADSP-21489 to ADSP-21573 and ADSP-SC573 

Hello Pingky,

Please see my response below.

Does family ADSP-SC573 have interface with external static memory like AMI for ADSP-21489? If not than how can we ensure interaction with external static memory (RD, WE, CS, A, D)?

>> Unfortunately, ADSP-SC573 family doesn't have any static memory like AMI available in the ADSP-21489. 

Just wondering what the main purpose customer is using external static memory? ADSP-SC573 has large on-chip L2 SRAM of 1MB

We have about 3-6 ADSP-21489 processors on the board. One of them is loading initializer program from Flash memory, that is reading programs for other processors from Flash memory and loads them through SPI-slave mode. After loading of satellites main processor is reloaded from the same Flash memory but already by working program. Can we organize a similar scheme with ADSP-SC573 board as master processor and ADSP-21573 as slave?

>> Yes, it supports both master and slave boot modes. See the image given below.

Since processor has 2 or 3 cores more than one programmer will be working on software development. How is

ROM code merged(code polling)? Each core has its own loaded file or each time all codes are compiling? Is

there possibility to watch this process “ live”?

>> For ADSP-SC573, there are three cores with an ARM core and two SHARC cores. The program can be developed individually for each core and integrate them finally and generate a single LDR file to booting processor.

Now we need to store several programs for one processor in ROM. When system starts one of the processors loads (in future - ARM core) and upon analysis of system configuration several additional processors are loaded  (in future - SHARC ADSP-SC573 core) from different ROM addresses. In this case how can we organize loading of different programs for SHARC cores with the same program for ARM core?

>> The boot ROM provides a mechanism through available non-volatile programmable memory (OTP on this processor) to customize different aspects of the boot process. These customizations include: overriding default boot-peripheral instance, overriding default peripheral-timing parameters and disabling boot modes.

Many of the utilities of the boot code are also available to the application. These utilities include features such as
copying memory, comparing memory, or loading another boot stream at runtime. The APIs may be used to help
ensure that application code is more compatible with future products. 

For more information please refer to  chapter 46 Boot ROM and Booting the Processor in the ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference manual (HRM)

For more details on available APIs, see the API Reference section in the HRM.

Hope this helps

Best Regards,

Jithul

Customer have another question:

The main target of the external parallel interface is connection FPGA and nvSRAM to store the event log (not distorted when power is off). How can these connections be formed? Working through a parallel port requires too much development effort.

It seems that  in the description of the processor  is a description of the SMC.

As I understood , SMC is a static memory controller.  is that the thing we need?