DAC to ADC configuration using AD1939

Hi Anil,

When converting from a fixed-point to a floating-point type, the result is the closest floating-point value to the operand and leads to some precision loss.

Please refer in the below VisualDSP++ help path:

C/C++ Compiler Manualfor SHARC® Processors > 1 Compiler > C/C++ Compiler Language Extensions > Compiler Built-In Functions > Fractional Built-In Functions

C/C++ Compiler Manualfor SHARC® Processors > 1 Compiler > Using default Fixed-Point Types > Data Type Conversions and Fixed-Point Types

Can you please let us know if you have experiencing any loss of precision when converting from fixed to float, or is the data completely different. So the we can guide appropriately

Regards,
Nandini C

Hi Nandini,

Thank you for the reply,

For example iam sending a sinewave from transmitter using DAC with 48k sampling rate and fc=1800Hz at tx_block_pointer the samples and plot which i observed both in software and oscilloscope getting similar,while at receiving end the after adc output that means fixed to floating point conversion hits completely different values but that values representing a sine wave but not the same frequency and sampling rate and values are often changing whenever i click the run option.the values are changing instantly suppose at trasmitter side for sinewave possitive half cycle repsenting 6 values then at receiver side it representing 4/5/6 and sometimes it starting with negative values..Hope you understood..if you are not able to understand i will try to send the snippets of waveform and values if possible i will try to add code snippets also.

Regards

Anil

Hi Nandini,

I also want to ask that sometimes number samples/cycle at transmitter side was not same at receiver side and i observed that the values around  0 are not able receive at receiver side.

for example at transmitter side if the values are 0.4564,0,58323,0.75234,0.0015234,0.000532.after DAC output

the values of 0.0015234,0.000532 was not able to recover after ADC output

all these when DAC connected to ADC

Regards

Anil

Hi Anil,

While analyzing the modulation_out values, we found that the issue is caused due to the overflow during the float_to_fix conversion.

To address this, we recommend enabling saturation mode by setting the ALUSAT bit in the MODE1 register before processing begins. When the ALUSAT bit in the MODE1 register is set (= 1), the ALU is in saturation mode. In this mode, positive fixed-point overflows return the maximum positive fixed-point number (0x7FFF FFFF), and negative overflows return the maximum negative number (0x8000 0000). If saturation mode is not set, an infinity input or a result that overflows returns a floating-point result of all 1s.

Alternatively, you can use the default fract fixed-point type to generate equivalent code. In this case, you can cast between fract and float types directly, without using a built-in conversion function. This cast behavior is independent of the rounding mode set in the MODE1 register, unlike the built-in conversion.

Below is sample code to cast the fract-typed argument to float type without using the built-in conversion.

#include <stdfix.h>

void fixed_to_float(float *output, const fract *input, int num) {
int i;
for (i = 0; i < num; i++) {
output[i] = input[i];
}
}

Could you please test this and let us know the results.

Additionally, the code currently configures the ADC and DAC for 8 channels. Please update the channel settings to ADC_CHANNELS_2 in the ADCCTRL2 register and DAC_CHANNELS_2 in the DACCTRL1 register. Hope you have only copied the left channel data to tx_block_pointer for testing purpose.

Regarding “I also want to ask that sometimes number samples/cycle at transmitter side was not same at receiver side and i observed that the values around 0 are not able receive at receiver side.”
>> Could you please clarify whether values around 0 are never received on the receiver side, or if this occurs intermittently?

Regards,
Nandini C

Hi Nandini,

Thank you for the reply,

Iam looking into this, I will update as soon as possible

Regards 

Anil

MEL_rx.zipMEL1_tx.zip

Hi Nandini,

Apologies for the delay

>> Could you please clarify whether values around 0 are never received on the receiver side, or if this occurs intermittently?

As discussed in earlier question similar problem encountered with when we transmit RRC coefficients. The result almost similar when we use both built-in conversion function and const fract function. At the receiver end the values are completely different and getting an offset(DC) value also(kindly check my intuition correct or not?). And my question why the values are not coming straight at the receiver end when transmit any data? To see that full cycle of values do we need to increase the receiver buffer size? or Is it because of circular buffer?

Here I am attaching the project files for both Tx and Rx and snapshots of tx_block_pointer and rx_block_pointer with received values you can check with it transmitter values which are in main function. Please kindly help in this regard.

>>To address this, we recommend enabling saturation mode by setting the ALUSAT bit 

when I am trying to set the ALUSAT bit the program getting halted and not running.

>>you can use the default fract fixed-point type to generate equivalent code.

Yes I tried the with fract function also the result is similar to built-in function output.

>>the code currently configures the ADC and DAC for 8 channels.

Yes i changed both in SPORT_TDM function and in ADSP21489_ezkit.h also nothing much changed

Regards

Anil

Hi Anil,

To assist you more effectively, could you please clarify the following points:

1.Has the sine wave clipping issue been resolved by setting the ALUSAT bit, or by using the default fractional fixed-point format?
2.Are you using a custom board or an EZ-KIT?
3.Are you using two EZ-KITs, where EZ-KIT 1 transmits data to a DAC, and the DAC output is connected via RCA cable to the ADC of EZ-KIT 2, with the data from EZ-KIT 2 being plotted?

Regards,
Nandini C

Hi Nandini,

>>1.Has the sine wave clipping issue been resolved by setting the ALUSAT bit, or by using the default fractional fixed-point format?

No,The issue not resolved..I replied in earlier answer also when I am trying to enable the ALUSAT bit the program getting halted not running.

>>2.Are you using a custom board or an EZ-KIT?

Iam using EZ-KIT ADSP21489 evaluation board only.

>>3.Are you using two EZ-KITs, where EZ-KIT 1 transmits data to a DAC, and the DAC output is connected via RCA cable to the ADC of EZ-KIT 2, with the data from EZ-KIT 2 being plotted?

yes the setup is placed like what you have mentioned...I replied in my previous answer with values and project files, because you asked a question regarding >>could you please clarify whether values around 0 are never received on the receiver side, or if this occurs intermittently?]on may 8,2025.

I replied with the answer on may 20,2025. could you please check in previous answer also.

I think i clarified what you have asked for.If any further clarifications needed please post.

Regards

Anil
 

Hi Anil,

We were able to replicate the behaviour on our side and are currently analyzing it. We will get back to you as soon as possible.

Regards,
Nandini.C

Hi Anil,

Regarding “ I also want to ask that sometimes number samples/cycle at transmitter side was not same at receiver side and i observed that the values around 0 are not able receive at receiver side.
for example at transmitter side if the values are 0.4564,0,58323,0.75234,0.0015234,0.000532.after DAC output the values of 0.0015234,0.000532 was not able to recover after ADC output. all these when DAC connected to ADC”
>> This behaviour is expected. Instead of comparing tx_block_pointer and rx_block_pointer, please verify the DAC output of Transmitter Ez-kit and DAC output of receiver EZ-Kit using an oscilloscope. Because DAC and ADC do not simply transfer the data, they perform analog reconstruction and sampling, which can introduce variations.

In the Transmitter, once tx_block_pointer is converted to fixed-point data format, it passed to the DAC. The DAC includes reconstruction filters and operates with an oversampling ratio of 4 in both 48 kHz and 96 kHz modes to reconstruct the analog signal. The analog output is then routed to the ADC via RCA connectors.

On the receiver, the ADC performs oversampling with an oversampling ratio of 128, supporting 48 kHz, 96 kHz, and 192 kHz modes. Although both the DAC and ADC operate at the same sampling rates, slight differences in their sampling instants can lead to discrepancies in the digital data.

Additionally, a digital high-pass filter can be switched in line with the ADCs under serial control to remove residual dc offsets. Could you please enable High-pass filter in ADC Control 0 Register?

To see that full cycle of values do we need to increase the receiver buffer size? or Is it because of circular buffer?
>> Yes, please increase the count in plot window to see the continuous data.

Regarding the clipping issue, could you please try with the attached project and let us know the results. We have enabled the ALUSAT bit and changed the cut-off frequency to 1500 to get the complete full cycles in 256 samples for continuous cos wave generation. In the DAC output, we can see the continuous signal without any clipping in the CRO.

MEL_June03.zip

Regards,
Nandini C

Hi Nandini,

Thank you for the reply,

 I had checked the file what you have sent on EZ-KIT its working..and for rest all questions were clarified  Thank you for the clarification,

>>a digital high-pass filter can be switched in line with the ADCs under serial control to remove residual dc offsets. Could you please enable High-pass filter in ADC Control 0 Register?

Yes i enable the highpass filter in 1939spi file..But I am not able to find any difference,anyway now its fine. could you please throw some light on this topic?

Hi Anil,

The ADCs in the AD1939 have inbuilt digital high-pass filter which have the cut off frequency of 1.4hz and used to remove dc offsets. This is useful in applications requiring flexible signal processing across different sampling rates.

Please refer the below link for the detailed information about the High Pass Filter in ADC: https://ez.analog.com/audio/f/q-a/580025/ad1937-adc-input/521122 

Hope this helps!

Regards,
Nandini C

Hi Anil,

The ADCs in the AD1939 have inbuilt digital high-pass filter which have the cut off frequency of 1.4hz and used to remove dc offsets. This is useful in applications requiring flexible signal processing across different sampling rates.

Please refer the below link for the detailed information about the High Pass Filter in ADC: https://ez.analog.com/audio/f/q-a/580025/ad1937-adc-input/521122 

Hope this helps!

Regards,
Nandini C