[Error el2011] Invalid memory range and/or width for memory 'SS4SH_CODEB'

Porting ADSP-21569 SS_App_Core1 to ADSP-21565, CCES build is fine. SS4G code and param are places in L2 as below:

   mem_L2_bw               { TYPE(BW RAM) START(0x20000000) END(0x2004ffff) WIDTH(8) }
   mem_L2UC_bw             { TYPE(BW RAM) START(0x200fa000) END(0x200fdfff) WIDTH(8) }
   mem_L2BC_bw             { TYPE(BW RAM) START(0x200fe000) END(0x200fffff) WIDTH(8) }

  #define MY_L2_UNCACHED_MEM mem_L2UC_bw
  #define MY_L2_CACHED_MEM   mem_L2_bw
   
   /*$VDSG<insert-new-memory-segments>                          */
   /* Text inserted between these $VDSG comments will be preserved */
   #if !defined(MY_SDRAM_SWCODE_MEM)
   /* 96 kB reserverd for SS4G code  */
   mem_L2_bw_SS4G_Code    { TYPE(BW RAM) START(0x20050000) END(0x200D7fff) WIDTH(8) }   
   #endif
   
   #if !defined(MY_SDRAM_DATA1_MEM)   
   /* 160 kB reserverd for SS4G data  */   
   mem_L2_bw_SS4G_Data    { TYPE(BW RAM) START(0x200D8000) END(0x200f9fff) WIDTH(8) }   
   #endif

However, when link-compile schematic in SigmaStudio Plus, Schematic DXE generation failed:

> Compilation Started...
> DiffDXESchematic_1: Compile Started - 00:04:31 AM ==========
> DiffDXESchematic_1: Mode: Single Core
> Framework_SH0.c .... : Successful!
> SSn_SH0.asm .... : Successful!
> FrameworkUtils_SH0.c .... : Successful!
> CModulesIntern_SH0.c .... : Successful!
> CModules_SH0.c .... : Successful!
> Param_SH0.c .... : Successful!
> SubProcess_SH0.c .... : Successful!
> Schematic DXE generation failed!

> [Error el2011]  Invalid memory range and/or width for memory 'SS4SH_CODEB'
> Block outside defined memory regions

> Linker finished with 1 error 
> cc3089: fatal error: Link failed (code:1)
> SH0 Memory allocation failed!
> Error - Memory allocation failed!
> Project Compilation failed

CCES 2.10 + SS4Sharc 4.7 does not reproduce this issue.

Does SigmaStudio Plus support ADSP-21565 ?

Yours

Totoro