Hello,
I'm using a 24.576 MHz MCLK input on Pin DAI0_04, which is routed to PCG A to generate the clocks for TDM8. The whole clock routing is working properly (checked with scope).
My DAC is connected to SPORT 2A and is working as it should (checked with the output of testdata and ) So DMA and SPORT config must be correct.
The ADC is connected to SPORT 4A, the MCU input to SPORT 7A. The settings are identical (despite the direction of data transfer). The clocks from PCG A are routed to DAI pins via CRS. From the output pins I routed to the SPORTS clk and fs inputs. The clock signals show up on the pins as expected.
The problem is: both registered SPORT callbacks (SPORT 2A and 7A) are not triggered (the counter "SPORT_CB_counter" is checked in the main loop and a print is output every 1000 cycles).
Am I missing something? Please have a short look at the code.
Kind regards,
Markus
//======= PCG Init ======= //Includes #include <services/pcg/adi_pcg.h> #include "Driver_PCG.h" #include "Driver_Debug.h" //Functions void PCG_Init(void){ //BCLK config TDM8 ADI_PCG_CLK_INFO PCG_CLK_Inf_TDM8 = { ADI_PCG_CLK_EXT, //Clock Source 2u, //Clock Divisor for 12.288 MHz false //External Trigger }; //FS config for 48 kHz, TDM8 ADI_PCG_FS_INFO PCG_FS_Inf_TDM8 = { ADI_PCG_FS_EXT, //Clock Source 512u, //Frame Sync Divisor 48 KHz 256u, //Pulse Width 1u, //Phase shift for edge sync = clk_div / 2 false, //External Trigger ADI_PCG_FSBYPASS_MODE_NORMAL //Bypass Mode normal }; //Init adi_pcg_Init(ADI_PCG_DEV_A, &PCG_CLK_Inf_TDM8, &PCG_FS_Inf_TDM8); } //======= SPU Init ======= //Includes #include <stdint.h> #include <stdio.h> #include <services/spu/adi_spu.h> #include "Driver_SPU.h" #include "Driver_SPORT.h" #include "Driver_Debug.h" //SPU IDs, p. #define UART0_SPU_PID 29 #define UART0_Rx_DMA_SPU 65 #define UART0_Tx_DMA_SPU 66 #define SPORT_0A_SPU 13 #define SPORT_0B_SPU 14 #define SPORT_1A_SPU 15 #define SPORT_1B_SPU 16 #define SPORT_2A_SPU 17 #define SPORT_2B_SPU 18 #define SPORT_3A_SPU 19 #define SPORT_3B_SPU 20 #define SPORT_4A_SPU 21 #define SPORT_4B_SPU 22 #define SPORT_5A_SPU 23 #define SPORT_5B_SPU 24 #define SPORT_6A_SPU 25 #define SPORT_6B_SPU 26 #define SPORT_7A_SPU 27 #define SPORT_7B_SPU 28 #define SPORT_0A_DMA_SPU 49 #define SPORT_0B_DMA_SPU 50 #define SPORT_1A_DMA_SPU 51 #define SPORT_1B_DMA_SPU 52 #define SPORT_2A_DMA_SPU 53 #define SPORT_2B_DMA_SPU 54 #define SPORT_3A_DMA_SPU 55 #define SPORT_3B_DMA_SPU 56 #define SPORT_4A_DMA_SPU 57 #define SPORT_4B_DMA_SPU 58 #define SPORT_5A_DMA_SPU 59 #define SPORT_5B_DMA_SPU 60 #define SPORT_6A_DMA_SPU 61 #define SPORT_6B_DMA_SPU 62 #define SPORT_7A_DMA_SPU 63 #define SPORT_7B_DMA_SPU 64 //Variables static uint8_t SpuMemory[ADI_SPU_MEMORY_SIZE]; static ADI_SPU_HANDLE hSpu; //SPU handle //SPORT - Make SPORTs to generate secure transactions //ADC eResult = adi_spu_EnableMasterSecure(hSpu, SPORT_4A_SPU, true); if(eResult != ADI_SPU_SUCCESS){ printf("Error: SPU Secure Transfer not possible! Errorcode: 0x%08X\n", eResult); } eResult = adi_spu_EnableMasterSecure(hSpu, SPORT_4A_DMA_SPU, true); if(eResult != ADI_SPU_SUCCESS){ printf("Error: SPU Secure Transfer not possible! Errorcode: 0x%08X\n", eResult); } //MCU eResult = adi_spu_EnableMasterSecure(hSpu, SPORT_7A_SPU, true); if(eResult != ADI_SPU_SUCCESS){ printf("Error: SPU Secure Transfer not possible! Errorcode: 0x%08X\n", eResult); } eResult = adi_spu_EnableMasterSecure(hSpu, SPORT_7A_DMA_SPU, true); if(eResult != ADI_SPU_SUCCESS){ printf("Error: SPU Secure Transfer not possible! Errorcode: 0x%08X\n", eResult); } //DAC eResult = adi_spu_EnableMasterSecure(hSpu, SPORT_2A_SPU, true); if(eResult != ADI_SPU_SUCCESS){ printf("Error: SPU Secure Transfer not possible! Errorcode: 0x%08X\n", eResult); } eResult = adi_spu_EnableMasterSecure(hSpu, SPORT_2A_DMA_SPU, true); if(eResult != ADI_SPU_SUCCESS){ printf("Error: SPU Secure Transfer not possible! Errorcode: 0x%08X\n", eResult); } //======= SRU Init ======= //Port Input Enable Control Register *pREG_PADS0_DAI0_IE = BITM_PADS_DAI0_IE_VALUE; *pREG_PADS0_DAI1_IE = BITM_PADS_DAI1_IE_VALUE; //---- MCLK Input ---- SRU(LOW, DAI0_PBEN04_I); //Set pinbuf to input SRU(DAI0_PB04_O, PCG0_EXTCLKA_I); //Route clock input to PCG A SRU(DAI0_PB04_O, PCG0_EXTCLKB_I); //Route clock input to PCG B //Route PCG A fs as trigger source to PCG B //SRU(PCG0_FSA_O, PCG0_SYNC_CLKB_I); //---- Clocks ---- //DAC - SPORT2A SRU(HIGH, DAI0_PBEN03_I); //Output SRU(PCG0_CLKA_O, DAI0_PB03_I); //PCG A clk to DAC MCLK pin SRU(HIGH, DAI0_PBEN06_I); //Output SRU(PCG0_CLKA_O, DAI0_PB06_I); //PCG A clk to DAC BCLK pin SRU(PCG0_CLKA_O, SPT2_ACLK_I); //PCG A clk to SPORT 2A SRU(HIGH, DAI0_PBEN02_I); //Output SRU(PCG0_FSA_O, DAI0_PB02_I); //PCG A fs to DAC LRCLK pin SRU(PCG0_FSA_O, SPT2_AFS_I); //PCG A clk to SPORT 2A //MCU - SPORT7A (CRS) SRU2(HIGH, DAI1_PBEN04_I); //Output SRU2(PCG0_CRS_CLKA_O, DAI1_PB04_I); //PCG A clk to MCU MCLK pin (CRS) SRU2(HIGH, DAI1_PBEN02_I); //Output SRU2(PCG0_CRS_CLKA_O, DAI1_PB02_I); //PCG A clk to MCU BCLK pin (CRS) SRU2(DAI1_PB02_O, SPT7_ACLK_I); //PCG A clk to SPORT 7A SRU2(HIGH, DAI1_PBEN01_I); //Output SRU2(PCG0_CRS_FSA_O, DAI1_PB01_I); //PCG A fs to MCU LRCLK pin (CRS) SRU2(DAI1_PB01_O, SPT7_AFS_I); //PCG A fs to SPORT 7A //ADC - SPORT4A SRU(HIGH, DAI0_PBEN12_I); //Output SRU(PCG0_CLKA_O, DAI0_PB12_I); //PCG A clk to ADC MCLK pin SRU(HIGH, DAI0_PBEN20_I); //Output SRU(PCG0_CLKA_O, DAI0_PB20_I); //PCG A clk to ADC BCLK pin SRU2(DAI1_PB02_O, SPT4_ACLK_I); //PCG A clk from MCU BCLK pin to SPORT 4A SRU(HIGH, DAI0_PBEN19_I); //Output SRU(PCG0_FSA_O, DAI0_PB19_I); //PCG A fs to ADC LRCLK pin SRU2(DAI1_PB01_O, SPT4_AFS_I); //PCG A fs from MCU LRCLK pin to SPORT 4A //---- Data pins ---- //ADC SRU2(LOW, DAI1_PBEN19_I); //Input SRU2(DAI1_PB19_O, SPT4_AD0_I); //SPORT 4A //MCU SRU2(LOW, DAI1_PBEN03_I); //Input SRU2(DAI1_PB03_O, SPT7_AD0_I); //SPORT 7A //DAC SRU(HIGH, DAI0_PBEN01_I); //Output SRU(SPT2_AD0_O, DAI0_PB01_I); //SPORT 2A //======= Driver SPORT ======= //Includes #include <stdint.h> #include <stdio.h> #include <string.h> #include <services/int/adi_int.h> #include <drivers/sport/adi_sport.h> #include "Driver_SPORT.h" #include "Driver_DMA.h" #include "Driver_Debug.h" #include <math.h> //Definitions //Variables //Memory required for SPORTs static uint8_t SPORTMemory0A[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory0B[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory1A[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory1B[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory2A[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory4A[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory5A[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory5B[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory6A[ADI_SPORT_MEMORY_SIZE]; static uint8_t SPORTMemory7A[ADI_SPORT_MEMORY_SIZE]; //SPORT Handles static ADI_SPORT_HANDLE hSPORT_0A = NULL; static ADI_SPORT_HANDLE hSPORT_0B = NULL; static ADI_SPORT_HANDLE hSPORT_1A = NULL; static ADI_SPORT_HANDLE hSPORT_1B = NULL; static ADI_SPORT_HANDLE hSPORT_2A_DAC = NULL; //DAC static ADI_SPORT_HANDLE hSPORT_4A_ADC = NULL; //ADC in static ADI_SPORT_HANDLE hSPORT_5A_DANTE = NULL; //DANTE in static ADI_SPORT_HANDLE hSPORT_5B = NULL; static ADI_SPORT_HANDLE hSPORT_6A_AES = NULL; //AES in static ADI_SPORT_HANDLE hSPORT_7A_MCU = NULL; //MCU in static volatile bool block_number = 0; ADI_CACHE_ALIGN int32_t DAC_Buffer1[BLOCKSIZE * TDM8_NB_CH] = {}; ADI_CACHE_ALIGN int32_t DAC_Buffer2[BLOCKSIZE * TDM8_NB_CH] = {}; ADI_CACHE_ALIGN int32_t ADC_Buffer1[BLOCKSIZE * TDM8_NB_CH] = {}; ADI_CACHE_ALIGN int32_t ADC_Buffer2[BLOCKSIZE * TDM8_NB_CH] = {}; ADI_CACHE_ALIGN int32_t MCU_Buffer1[BLOCKSIZE * TDM8_NB_CH] = {}; ADI_CACHE_ALIGN int32_t MCU_Buffer2[BLOCKSIZE * TDM8_NB_CH] = {}; //Function prototypes void SPORT4A_ADC_Cb(void *pAppHandle, uint32_t nEvent, void *pArg); void SPORT2A_DAC_Cb(void *pAppHandle, uint32_t nEvent, void *pArg); void SPORT7A_MCU_Cb(void *pAppHandle, uint32_t nEvent, void *pArg); void FillDACBufferWithTestdata(void); //Function definitions void SPORT_Init(void){ ADI_SPORT_RESULT eResult; //FillDACBufferWithTestdata(); //---- SPORT Device 4A - ADC ---- eResult = adi_sport_Open(4u, ADI_HALF_SPORT_A, ADI_SPORT_DIR_RX, ADI_SPORT_MC_MODE, SPORTMemory4A, ADI_SPORT_MEMORY_SIZE, &hSPORT_4A_ADC); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config data: datatype zero fill, word length 32 bit, MSB first, DMA packing disabled, right-justified disabled eResult = adi_sport_ConfigData(hSPORT_4A_ADC, ADI_SPORT_DTYPE_ZERO_FILL, 31u, false, false, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config clock: internal clock ratio (ignored), use external clock, sample data on rising edge, disable gated clock eResult = adi_sport_ConfigClock(hSPORT_4A_ADC, 0u, false, false, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config fs: slot width 32 bit, fs required, use external fs, data-independent fs (ignored in MC mode), active low fs, early fs, edge sensitive fs eResult = adi_sport_ConfigFrameSync(hSPORT_4A_ADC, 31u, true, false, true, false, false, true); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config MC: fs delay 1 bclk, 8 slots, window start 0, mc dma data packing disabled eResult = adi_sport_ConfigMC(hSPORT_4A_ADC, 1u, 7u, 0u, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config channels: starting ch nb 0, end ch nb 7 eResult = adi_sport_SelectChannel(hSPORT_4A_ADC, 0u, 7u); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} DEBUG_PRINT("SPORT 4A opened and configured\n"); //Register SPORT Callback function eResult = adi_sport_RegisterCallback(hSPORT_4A_ADC, SPORT4A_ADC_Cb, NULL); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} DEBUG_PRINT("SPORT 4A cb registered\n"); //---- SPORT Device 2A - DAC ---- eResult = adi_sport_Open(2u, ADI_HALF_SPORT_A, ADI_SPORT_DIR_TX, ADI_SPORT_MC_MODE, SPORTMemory2A, ADI_SPORT_MEMORY_SIZE, &hSPORT_2A_DAC); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config data: datatype zero fill, word length 32 bit, MSB first, DMA packing disabled, right-justified disabled eResult = adi_sport_ConfigData(hSPORT_2A_DAC, ADI_SPORT_DTYPE_ZERO_FILL, 31u, false, false, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config clock: internal clock ratio (ignored), use external clock, sample data on rising edge, disable gated clock eResult = adi_sport_ConfigClock(hSPORT_2A_DAC, 0u, false, false, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config fs: slot width 32 bit, fs required, use external fs, data-independent fs (ignored in MC mode), active low fs, early fs, edge sensitive fs eResult = adi_sport_ConfigFrameSync(hSPORT_2A_DAC, 31u, true, false, true, false, false, true); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config MC: fs delay 1 bclk, 8 slots, window start 0, mc dma data packing disabled eResult = adi_sport_ConfigMC(hSPORT_2A_DAC, 1u, 7u, 0u, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config channels: starting ch nb 0, end ch nb 7 eResult = adi_sport_SelectChannel(hSPORT_2A_DAC, 0u, 7u); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} DEBUG_PRINT("SPORT 2A opened and configured\n"); //---- SPORT Device 7A - MCU ---- eResult = adi_sport_Open(7u, ADI_HALF_SPORT_A, ADI_SPORT_DIR_RX, ADI_SPORT_MC_MODE, SPORTMemory7A, ADI_SPORT_MEMORY_SIZE, &hSPORT_7A_MCU); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config data: datatype zero fill, word length 32 bit, MSB first, DMA packing disabled, right-justified disabled eResult = adi_sport_ConfigData(hSPORT_7A_MCU, ADI_SPORT_DTYPE_ZERO_FILL, 31u, false, false, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config clock: internal clock ratio (ignored), use external clock, sample data on rising edge, disable gated clock eResult = adi_sport_ConfigClock(hSPORT_7A_MCU, 0u, false, false, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config fs: slot width 32 bit, fs required, use external fs, data-independent fs (ignored in MC mode), active low fs, early fs, edge sensitive fs eResult = adi_sport_ConfigFrameSync(hSPORT_7A_MCU, 31u, true, false, true, false, false, true); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config MC: fs delay 1 bclk, 8 slots, window start 0, mc dma data packing disabled eResult = adi_sport_ConfigMC(hSPORT_7A_MCU, 1u, 7u, 0u, false); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} //Config channels: starting ch nb 0, end ch nb 7 eResult = adi_sport_SelectChannel(hSPORT_7A_MCU, 0u, 7u); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} DEBUG_PRINT("SPORT 7A opened and configured\n"); //Register SPORT Callback function eResult = adi_sport_RegisterCallback(hSPORT_7A_MCU, SPORT7A_MCU_Cb, NULL); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} DEBUG_PRINT("SPORT 7A cb registered\n"); //Init peripheral DMA descriptors PDMA_Init(); //---- Init first DMA transfer ---- eResult = adi_sport_DMATransfer(hSPORT_4A_ADC, &DMA_Desc_ADC_1, DMA_NUM_DESC, ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} eResult = adi_sport_DMATransfer(hSPORT_2A_DAC, &DMA_Desc_DAC_1, DMA_NUM_DESC, ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} eResult = adi_sport_DMATransfer(hSPORT_7A_MCU, &DMA_Desc_MCU_1, DMA_NUM_DESC, ADI_PDMA_DESCRIPTOR_LIST, ADI_SPORT_CHANNEL_PRIM); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT Error! Errorcode: 0x%08X\n", eResult);} DEBUG_PRINT("SPORT DMA started\n"); //---- Enable data transfer ---- eResult = adi_sport_Enable(hSPORT_4A_ADC, true); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT 4A Error! Errorcode: 0x%08X\n", eResult);} eResult = adi_sport_Enable(hSPORT_2A_DAC, true); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT 2A Error! Errorcode: 0x%08X\n", eResult);} eResult = adi_sport_Enable(hSPORT_7A_MCU, true); if(eResult != ADI_SPORT_SUCCESS) {DEBUG_PRINT("SPORT 7A Error! Errorcode: 0x%08X\n", eResult);} DEBUG_PRINT("SPORTs enabled\n"); } volatile uint32_t SPORT_CB_counter = 0; void SPORT7A_MCU_Cb(void *pAppHandle, uint32_t nEvent, void *pArg){ SPORT_CB_counter++; uint8_t offset = 0; switch (nEvent){ case ADI_SPORT_HW_ERR_PRIMARY_CHNL_OVERFLOW: //Rx mode break; case ADI_SPORT_HW_ERR_FS: break; case ADI_SPORT_HW_ERR_DMA: break; case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED: //Copy ADC buf to DAC buf if(block_number == 0){ //memcpy(DAC_Buffer1, ADC_Buffer1, (BLOCKSIZE * TDM8_NB_CH * 4)); for(uint16_t i=0; i < (BLOCKSIZE * TDM8_NB_CH); i+=8) { DAC_Buffer1[i] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+1] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+2] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+3] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+4] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+5] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+6] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+7] = ADC_Buffer1[i+offset]; } } else{ //memcpy(DAC_Buffer2, ADC_Buffer2, (BLOCKSIZE * TDM8_NB_CH * 4)); for(uint16_t i=0; i < (BLOCKSIZE * TDM8_NB_CH); i+=8) { DAC_Buffer2[i] = ADC_Buffer2[i]; DAC_Buffer2[i+1] = ADC_Buffer2[i]; DAC_Buffer2[i+2] = ADC_Buffer2[i]; DAC_Buffer2[i+3] = ADC_Buffer2[i]; DAC_Buffer2[i+4] = ADC_Buffer2[i]; DAC_Buffer2[i+5] = ADC_Buffer2[i]; DAC_Buffer2[i+6] = ADC_Buffer2[i]; DAC_Buffer2[i+7] = ADC_Buffer2[i]; } } block_number = !block_number; break; default: break; } } void SPORT4A_ADC_Cb(void *pAppHandle, uint32_t nEvent, void *pArg){ SPORT_CB_counter++; uint8_t offset = 0; switch (nEvent){ case ADI_SPORT_HW_ERR_PRIMARY_CHNL_OVERFLOW: //Rx mode break; case ADI_SPORT_HW_ERR_FS: break; case ADI_SPORT_HW_ERR_DMA: break; case ADI_SPORT_EVENT_RX_BUFFER_PROCESSED: //Copy ADC buf to DAC buf if(block_number == 0){ //memcpy(DAC_Buffer1, ADC_Buffer1, (BLOCKSIZE * TDM8_NB_CH * 4)); for(uint16_t i=0; i < (BLOCKSIZE * TDM8_NB_CH); i+=8) { DAC_Buffer1[i] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+1] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+2] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+3] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+4] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+5] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+6] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+7] = ADC_Buffer1[i+offset]; } } else{ //memcpy(DAC_Buffer2, ADC_Buffer2, (BLOCKSIZE * TDM8_NB_CH * 4)); for(uint16_t i=0; i < (BLOCKSIZE * TDM8_NB_CH); i+=8) { DAC_Buffer2[i] = ADC_Buffer2[i]; DAC_Buffer2[i+1] = ADC_Buffer2[i]; DAC_Buffer2[i+2] = ADC_Buffer2[i]; DAC_Buffer2[i+3] = ADC_Buffer2[i]; DAC_Buffer2[i+4] = ADC_Buffer2[i]; DAC_Buffer2[i+5] = ADC_Buffer2[i]; DAC_Buffer2[i+6] = ADC_Buffer2[i]; DAC_Buffer2[i+7] = ADC_Buffer2[i]; } } block_number = !block_number; break; default: break; } } void SPORT2A_DAC_Cb(void *pAppHandle, uint32_t nEvent, void *pArg){ SPORT_CB_counter++; uint8_t offset = 0; switch (nEvent){ case ADI_SPORT_HW_ERR_PRIMARY_CHNL_OVERFLOW: //Rx mode break; case ADI_SPORT_HW_ERR_FS: break; case ADI_SPORT_HW_ERR_DMA: break; case ADI_SPORT_EVENT_TX_BUFFER_PROCESSED: //Copy ADC buf to DAC buf if(block_number == 0){ //memcpy(DAC_Buffer1, ADC_Buffer1, sizeof(DAC_Buffer1)); for(uint16_t i=0; i < (BLOCKSIZE * TDM8_NB_CH); i+=8) { DAC_Buffer1[i] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+1] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+2] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+3] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+4] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+5] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+6] = ADC_Buffer1[i+offset]; DAC_Buffer1[i+7] = ADC_Buffer1[i+offset]; } } else{ //memcpy(DAC_Buffer2, ADC_Buffer2, sizeof(DAC_Buffer2)); for(uint16_t i=0; i < (BLOCKSIZE * TDM8_NB_CH); i+=8) { DAC_Buffer2[i] = ADC_Buffer2[i+offset]; DAC_Buffer2[i+1] = ADC_Buffer2[i+offset]; DAC_Buffer2[i+2] = ADC_Buffer2[i+offset]; DAC_Buffer2[i+3] = ADC_Buffer2[i+offset]; DAC_Buffer2[i+4] = ADC_Buffer2[i+offset]; DAC_Buffer2[i+5] = ADC_Buffer2[i+offset]; DAC_Buffer2[i+6] = ADC_Buffer2[i+offset]; DAC_Buffer2[i+7] = ADC_Buffer2[i+offset]; } } block_number = !block_number; break; default: break; } } void FillDACBufferWithTestdata(void){ double gain_dB = -3; double gain = pow(10.0, ((double)gain_dB/20.0)); bool highorlow = 1; for(uint16_t i=0; i < (BLOCKSIZE * TDM8_NB_CH); i+=8) { if(highorlow){ DAC_Buffer1[i] = (int32_t)((double)(0x7FFFFFFF) * gain); DAC_Buffer1[i+1] = DAC_Buffer1[i]; DAC_Buffer1[i+2] = DAC_Buffer1[i]; DAC_Buffer1[i+3] = DAC_Buffer1[i]; DAC_Buffer1[i+4] = DAC_Buffer1[i]; DAC_Buffer1[i+5] = DAC_Buffer1[i]; DAC_Buffer1[i+6] = DAC_Buffer1[i]; DAC_Buffer1[i+7] = DAC_Buffer1[i]; } else{ DAC_Buffer1[i] = 0; DAC_Buffer1[i+1] = 0; DAC_Buffer1[i+2] = 0; DAC_Buffer1[i+3] = 0; DAC_Buffer1[i+4] = 0; DAC_Buffer1[i+5] = 0; DAC_Buffer1[i+6] = 0; DAC_Buffer1[i+7] = 0; } highorlow = !highorlow; } memcpy(DAC_Buffer2, DAC_Buffer1, (BLOCKSIZE * TDM8_NB_CH * 4)); DEBUG_PRINT("DAC buffer filled with testdata\n"); } //======== DMA Init ========= //Include #include <stdint.h> #include <stdio.h> #include "Driver_DMA.h" #include "Driver_SPORT.h" #include "Driver_Debug.h" //Descriptors ADI_CACHE_ALIGN ADI_PDMA_DESC_LIST DMA_Desc_ADC_1 = {}; ADI_CACHE_ALIGN ADI_PDMA_DESC_LIST DMA_Desc_ADC_2 = {}; ADI_CACHE_ALIGN ADI_PDMA_DESC_LIST DMA_Desc_DAC_1 = {}; ADI_CACHE_ALIGN ADI_PDMA_DESC_LIST DMA_Desc_DAC_2 = {}; ADI_CACHE_ALIGN ADI_PDMA_DESC_LIST DMA_Desc_MCU_1 = {}; ADI_CACHE_ALIGN ADI_PDMA_DESC_LIST DMA_Desc_MCU_2 = {}; void PDMA_Init(void){ //2A //DAC buffer DMA_Desc_DAC_1.pStartAddr = DAC_Buffer1; DMA_Desc_DAC_1.Config = ENUM_DMA_CFG_XCNT_INT; // | ENUM_DMA_CFG_TRGWAIT; DMA_Desc_DAC_1.XCount = BLOCKSIZE * TDM8_NB_CH; DMA_Desc_DAC_1.XModify = 4; DMA_Desc_DAC_1.YCount = 0; DMA_Desc_DAC_1.YModify = 0; DMA_Desc_DAC_1.pNxtDscp = &DMA_Desc_DAC_2; DMA_Desc_DAC_2.pStartAddr = DAC_Buffer2; DMA_Desc_DAC_2.Config = ENUM_DMA_CFG_XCNT_INT; DMA_Desc_DAC_2.XCount = BLOCKSIZE * TDM8_NB_CH; DMA_Desc_DAC_2.XModify = 4; DMA_Desc_DAC_2.YCount = 0; DMA_Desc_DAC_2.YModify = 0; DMA_Desc_DAC_2.pNxtDscp = &DMA_Desc_DAC_1; //4A //ADC buffer DMA_Desc_ADC_1.pStartAddr = ADC_Buffer1; DMA_Desc_ADC_1.Config = ENUM_DMA_CFG_XCNT_INT; // | ENUM_DMA_CFG_TRGWAIT; DMA_Desc_ADC_1.XCount = BLOCKSIZE * TDM8_NB_CH; DMA_Desc_ADC_1.XModify = 4; DMA_Desc_ADC_1.YCount = 0; DMA_Desc_ADC_1.YModify = 0; DMA_Desc_ADC_1.pNxtDscp = &DMA_Desc_ADC_2; DMA_Desc_ADC_2.pStartAddr = ADC_Buffer2; DMA_Desc_ADC_2.Config = ENUM_DMA_CFG_XCNT_INT; DMA_Desc_ADC_2.XCount = BLOCKSIZE * TDM8_NB_CH; DMA_Desc_ADC_2.XModify = 4; DMA_Desc_ADC_2.YCount = 0; DMA_Desc_ADC_2.YModify = 0; DMA_Desc_ADC_2.pNxtDscp = &DMA_Desc_ADC_1; //7A //MCU buffer DMA_Desc_MCU_1.pStartAddr = MCU_Buffer1; DMA_Desc_MCU_1.Config = ENUM_DMA_CFG_XCNT_INT; // | ENUM_DMA_CFG_TRGWAIT; DMA_Desc_MCU_1.XCount = BLOCKSIZE * TDM8_NB_CH; DMA_Desc_MCU_1.XModify = 4; DMA_Desc_MCU_1.YCount = 0; DMA_Desc_MCU_1.YModify = 0; DMA_Desc_MCU_1.pNxtDscp = &DMA_Desc_MCU_2; DMA_Desc_MCU_2.pStartAddr = MCU_Buffer2; DMA_Desc_MCU_2.Config = ENUM_DMA_CFG_XCNT_INT; DMA_Desc_MCU_2.XCount = BLOCKSIZE * TDM8_NB_CH; DMA_Desc_MCU_2.XModify = 4; DMA_Desc_MCU_2.YCount = 0; DMA_Desc_MCU_2.YModify = 0; DMA_Desc_MCU_2.pNxtDscp = &DMA_Desc_MCU_1; }