Hello,
I use an external oscillator to supply a 24.576 MHz clock as an input for PCG A and B. See the code below:
//BCLK config TDM16
ADI_PCG_CLK_INFO PCG_CLK_Inf_TDM16 =
{
ADI_PCG_CLK_EXT, //Clock Source
1u, //Clock Divisor for 24.576 MHz
false //External Trigger
};
//BCLK config TDM8
ADI_PCG_CLK_INFO PCG_CLK_Inf_TDM8 =
{
ADI_PCG_CLK_EXT, //Clock Source
2u, //Clock Divisor for 12.288 MHz
false //External Trigger
};
//FS config for 48 kHz
ADI_PCG_FS_INFO PCG_FS_Inf =
{
ADI_PCG_FS_EXT, //Clock Source
512u, //Frame Sync Divisor 48 KHz
256u, //Pulse Width
0u, //Phase
false, //External Trigger
ADI_PCG_FSBYPASS_MODE_NORMAL //Bypass Mode normal
};
//Init
adi_pcg_Init(ADI_PCG_DEV_A, &PCG_CLK_Inf_TDM8, &PCG_FS_Inf);
adi_pcg_Init(ADI_PCG_DEV_B, &PCG_CLK_Inf_TDM16, &PCG_FS_Inf);
Clocks are working (checked with the scope). Both clocks are divided from the same input and therefore are working on the same timebase by default.
The question is, because the init functions of the clocks are called one after the other, could there be a time difference between the edges of the resulting clock signals?
Are the clocks sychronized internally?
How to ensure that the edges of both clocks are always (!) 100% synched? Is there an option to start the clocks with a trigger source like it is possible with SPORTS?
I just found the option to use an external trigger source clock, but that is not what I am searching for. I just want to start the clocks at the same time.
Kind regards,
Markus
