Hi,
I am trying to implement reads and writes to external memory (SDRAM) via multiple dma chains on a 21489 in assembly. There is an example in the manual but this only explains how to change the direction on the fly and seems to be constantly cycling through the two TCBs.
What I want to do is:
Read two memory blocks from SDRAM => prepare chain of two TCBs
Load first TCB to CECP0
Do something else
poll DMAC0 (look for CHS and DMAS bits)
Do something else
Read two memory blocks from SDRAM => prepare chain of two TCBs
Load first TCB to CECP0
Do something else
poll DMAC0 (look for CHS and DMAS bits)
Do something else
and so on.
My question is, is it enough to configure DMAC0 at the beginning only and the transfers are triggered whenever I write to CPEC0 register?
Or do I have to clear DMAC0 after a chain has finished and reinit it before I start the next chain?
And what is the correct way to poll the DMAC0? Is it right to look for CHS + DMAS? I don't want to go via interrupts.
Raphael
fixed some typos
[edited by: rkn at 10:37 PM (GMT -4) on 13 Oct 2022]