I’m using the ADSP 21469 EZ-Board Evaluation System and writing to the AMI bus and configuring AMICTL3.
I’m writing to a USB FIFO that requires a WRITE low pulse of 50 nsec min and then must remain high for 70nsec min (Bus Hold Cycle at end of WRITE) before executing the next WRITE low pulse.
I thought that using the CLKCFG[1:0] would change the Write Pulse width, but it doesn’t seem to make a difference whether it’s (0,1) for 16:1 CLK: Core or (0,0) 6:1.
Here are the parameters I’m using:
*pAMICTL3 = (AMIEN | BW8 | PKDIS | WS31 | HC7 | PREDIS | RHC7);
Currently I’m measuring clock high to be 36nsec when measured with an oscilloscope. The WRITE pulse low is 138nsec.
Is there another way to increase the Bus Hold Cycle at the end of a WRITE pulse?