Codec Configuration Registers.

Hi Hermione

For further assistance, can you please specify which processor you're using.

Regards,
Anand Selvaraj.

Dear Anand,

Please reply!

We are awaiting answers .

Dear Anand !

Please respond to the query above ...

I wonder why it takes so long to get a response.

Is there anywhere else i can look gor some quick answers.

Please support on this and queries further

Hi Hermione

Apologies for the delay
 
Please find the code for Audio passthrough  I2S mode, configuring PCG to provide clock both ADC and DAC .
Also please note that, If it is a custom board its recommended to use the suggested loop filters (refer: Figure 8) for DLRCLK , which is mentioned under "TYPICAL APPLICATION CIRCUITS" in ADAU1962A Datasheet Page:13. and Figure 15 which is under "PLL AND CLOCK" in ADAU1979 datasheet page:13

codec.zip
Regards,
Anand Selvaraj.

Dear Anand

Thank you that was supportive.

Meanwhile i am using the EV SOM Board and the problem is that i need to check SPDIF in to Analog Out .

Can you please share the SRU routing for 2ch SPDIF in to 8 ch DAC out .

Please 

Regards,

Hermione 

Hi Hermione,

Can you refer the Spdif_ASRC_DAC_Passthorugh code from BSP for the SRU connection.              
                                                                                                                                                                                                                                                                                           
In that, the example as Following connections are done using SRU.

1. SRU(SPDIF0_RX_FS_O,SRC0_FS_IP_I);        // SPDIF0 RX Clock (output) ----> ASRC clock (input)
2. SRU(SPDIF0_RX_CLK_O,SRC0_CLK_IP_I); // SPDIF0 RX Frame Sync (output) ----> ASRC Frame Sync (input)
3. SRU(SPDIF0_RX_DAT_O,SRC0_DAT_IP_I);  // SPDIF0 RX Data (output) ----> ASRC Data (input)
4. SRU(PCG0_FSA_O,SRC0_FS_OP_I);              //  PCG Frame Sync (output) ----> ASRC Frame Sync (output)                                                           
5. SRU(PCG0_CLKA_O,SRC0_CLK_OP_I);       //  PCG Clock (output) ----> ASRC clock (output)                                                                  
6. SRU(DAI0_CRS_PB03_O,PCG0_EXTCLKA_I); //  DAI_PIN03 (External clock)(output) ----> PCG Clock Input source (input)
7. SRU(PCG0_FSA_O,SPT0_BFS_I);                    // PCG Frame Sync (output) ----> SPORT 0B Frame Sync(input)
8. SRU(PCG0_CLKA_O,SPT0_BCLK_I);             //  PCG Clock (output) ----> SPORT 0B Clock (input)
9. SRU(SRC0_DAT_OP_O,SPT0_BD0_I);            //   ASRC Data out (output) ----> SPORT0B D0 (input)                                                             
10. SRU2(PCG0_CRS_CLKA_O ,DAI1_PB05_I);    //  PCG clock (output) ----> DAC clock (DAI1_PIN05)(input)                                                                     
11. SRU2(PCG0_CRS_FSA_O ,DAI1_PB04_I);       //  PCG Frame Sync (output) ----> DAC Frame Sync (DAI1_PIN04)(input)                                                                
12. SRU2(DAI1_PB05_O  ,SPT4_ACLK_I);           //  PCG Clock (output) ----> SPORT 4A Clock (input)   
13. SRU2(DAI1_PB04_O ,SPT4_AFS_I);                //  PCG Frame Sync (output) ----> SPORT 4A Frame Sync(input)
14. SRU2(SPT4_AD0_O,DAI1_PB01_I);                //  SPORT 4A D0 (output) ----> DAC data (input)
15. SRU(DAI0_PB09_O,SPDIF0_RX_I);                 //  SPDIF_Rx        
                                                           
with this as reference, please modify SRU as per your requirement.   
If still you are facing issue, please explain your connection with Block diagram. Like how you are going to connect the peripherals.

Regards,
Anand Selvaraj.

Dear Anand ,

In the code you sent me can you cross check the DAC Control 0 and 1 registers ?

It seems DAC is still programmed as Master?

Regards,

Hermione

Hi Hermione,

Below lines used in the project that we sent to change the clock source of DAC from LRCLK instead of Master clock:

Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x01);  // 1 is written to power up the IC

Write_TWI_8bit_Reg(ADAU1962_PLL_CTL_CTRL0,0x45); //  ADAU1962a clock can be either Phase-locked loop (PLL) generated or direct master clock. By configuring as 45, the on-board PLL derive the internal master clock from an external left-right frame clock (LRCLK)

Also, you can refer the SRU config:              
                                                                                                                                                 
SRU2(DAI1_PB03_O, PCG0_EXTCLKC_I); // 24.576MHz given to PCG input clock  

SRU2(PCG0_CLKC_O ,DAI1_PB05_I); // Here PCG clk is given to DLRclk of DAC

Regards,
Anand Selvaraj.

Dear Anand ! 

I am still not able to get analog out .

My design is as follows: 

2ch S/PDIF in (I2S) -> SPORT 4B(I2S) -> SPORT 4A(I2S)-> DAC out(I2S) .

DAC is slaved off using PCG C .

Can you share what needs to be taken care while SRU Routing .

I am guessing that is the only mismatch for no output on DAC

Also in SOM board any Switch Config for SpDif needs handling ????

Hi Hermione,

Can you please confirm that you are using ADSP-21569 SOM board with carrier?

Please refer the "SPDIF_ASRC_DAC_AudioPassthrough" code  in EV-2156x_EZ-KIT BSP package.

This example demonstrates the usage of the ADAU1962a DAC with ASRC & SPDIF interface in I2S mode.  SPDIF Rx receives the analog data(audio stream) from SPDIF streamer. SPDIF out CLK,FS and data is fed to the ASRC Input. PCG is configured to use 24.576 Mhz External clock as source and PCG output clock & FS is fed to ASRC Output(at 192KHz). SPORT 0B is configured as Rx which receives data from ASRC output. SPORT 4A is configured as Tx which sends out the audio data to ADAU1962a DAC.   PCG output clock & FS is fed to SPORT and DAC.

You can refer the SRU connections, Hardware Setup & External connections in Readme file. Also, this example includes the soft config switches for both SOM and carrier board.

Download  BSP using below link:
download.analog.com/.../ADI_EV-2156x_EZ-KIT-Rel1.0.1.exe

After installation: Analog Devices\EV-2156x_EZ-KIT-Rel1.0.1\EV-2156x_EZ-KIT\Examples\drivers\adc\SPDIF_ASRC_DAC_AudioPassthrough

Regards,
Anand Selvaraj.

Dear Anand ,

Well i think this is taking just too much time to verify something very basic and simple . So let me try and put things in perspective so you can help me better .

Firstly yes I am currently on the EV SOM CRR EZKIT . I am on CCES 2.9

Secondly , the example code you just referred to me works but with the following problem: 

1. I am unable to change the default used PCGA to PCG C .

2. The PLL Ctrl registers are set to 0x45 and 0x22 and DAC CTRL 0 Is set to 0x05? Can you explain these register settings .

3 In the example code DAI0PIN03 is crossed and fed to PCG A , but if  i am directly feeding DAI1PIN03 to PCC C, but just when i change this in SRU Routing output stops ...why ?

4. SPDIF does not seem to get enabled both Digital and Optical...

What exact lines of Code can enable the SPDIF in this EZKIT .

So far my assumptions were that the softconfig U6 for SPDIF DIGITAL EN must be sufficient but seems there is something i am missing 

5 Finally i will layout what i am trying to do so you can find outay e where the problem is : 

S/PDIF IN (2ch I2S) -Rx SPORT -> TX SPORT ->DAC OUT(2ch I2S) ...

The clocking part is a problem ????

Because the SPDIF will have its own I2S clock derived at Pin09 .

But the Rx Tx SPORTs and DAC will be clocked by PCG C???

Is that not feasible .

Regards,

Hermione 

Hi Hermione,

Apologies for the delay.

Please find the SRU connections for PCG C.

    /* SPDIF1 RX to ASRC Input */

         SRU2(SPDIF1_RX_FS_O,SRC7_FS_IP_I);
        SRU2(SPDIF1_RX_CLK_O,SRC7_CLK_IP_I);
        SRU2(SPDIF1_RX_DAT_O,SRC7_DAT_IP_I);

    /* PCG clock/FS to ASRC clock*/
        SRU2(PCG0_FSC_O,SRC7_FS_OP_I);
        SRU2(PCG0_CLKC_O,SRC7_CLK_OP_I);

    /* External clock to PCG input*/
    SRU2(DAI1_PB03_O,PCG0_EXTCLKC_I);

    /* PCG out to SPORT0B input*/

    SRU(DAI0_CRS_PB05_O, SPT0_BCLK_I);   //PCG CLOCK AND FS GIVEN TO PB5 AND PB4 OF DAI1. SO THE CRS CONNECTION OF RESPECTED PIN GIVEN HERE.
    SRU(DAI0_CRS_PB04_O, SPT0_BFS_I);

    /* ASRC data to SPORT 0B*/
    SRU(SRC7_CRS_DAT_OP_O,SPT0_BD0_I);   //OP DATA OF SRC7 IS CROSS CONNECTED AND GIVEN TO SPT0

    /* PCG clock to DAC clock*/
    SRU2(PCG0_CLKC_O ,DAI1_PB05_I);
    SRU2(HIGH,DAI1_PBEN05_I);

    /* PCG FS to DAC FS*/
    SRU2(PCG0_FSC_O ,DAI1_PB04_I);
    SRU2(HIGH,DAI1_PBEN04_I);

    /* PCG clk/fs to SPORT4*/
    SRU2(DAI1_PB05_O  ,SPT4_ACLK_I);
    SRU2(DAI1_PB04_O ,SPT4_AFS_I);

    /*Sport data to DAC data*/
    SRU2(SPT4_AD0_O,DAI1_PB01_I);
    SRU2(HIGH,DAI1_PBEN01_I);

    /*SPDIF Rx*/
    SRU(LOW,DAI0_PBEN09_I);
    SRU(HIGH,DAI0_PBEN03_I);              // RAC_O ---> DAI0_PB09_I ---> DAI0_PB03_I ---> DAI0_PB03_O ---> DAI1_CRS_PB03_O ---> SPDIF_RX_
    SRU(DAI0_PB09_O,DAI0_PB03_I);
    SRU2(DAI1_CRS_PB03_O,SPDIF1_RX_I);

About 0x45

>>> Here 4 denotes that PLL input is from DLR clk
>>>And 5 denotes the Master clock select and Power up the Master

About 0x22

>>> denotes the sample rate frequency is 128/176.4/192 KHz and muted channels

To know more about register settings please refer the ADAU 1962 Datasheet page:25 and 30
www.analog.com/.../ADAU1962.pdf

Also Please refer the Loop filter configurations recommended for DLR clk input in page:13 of ADAU1962 Datasheet

Regards,
Anand Selvaraj.

Hi Hermione,

Apologies for the delay.

Please find the SRU connections for PCG C.

    /* SPDIF1 RX to ASRC Input */

         SRU2(SPDIF1_RX_FS_O,SRC7_FS_IP_I);
        SRU2(SPDIF1_RX_CLK_O,SRC7_CLK_IP_I);
        SRU2(SPDIF1_RX_DAT_O,SRC7_DAT_IP_I);

    /* PCG clock/FS to ASRC clock*/
        SRU2(PCG0_FSC_O,SRC7_FS_OP_I);
        SRU2(PCG0_CLKC_O,SRC7_CLK_OP_I);

    /* External clock to PCG input*/
    SRU2(DAI1_PB03_O,PCG0_EXTCLKC_I);

    /* PCG out to SPORT0B input*/

    SRU(DAI0_CRS_PB05_O, SPT0_BCLK_I);   //PCG CLOCK AND FS GIVEN TO PB5 AND PB4 OF DAI1. SO THE CRS CONNECTION OF RESPECTED PIN GIVEN HERE.
    SRU(DAI0_CRS_PB04_O, SPT0_BFS_I);

    /* ASRC data to SPORT 0B*/
    SRU(SRC7_CRS_DAT_OP_O,SPT0_BD0_I);   //OP DATA OF SRC7 IS CROSS CONNECTED AND GIVEN TO SPT0

    /* PCG clock to DAC clock*/
    SRU2(PCG0_CLKC_O ,DAI1_PB05_I);
    SRU2(HIGH,DAI1_PBEN05_I);

    /* PCG FS to DAC FS*/
    SRU2(PCG0_FSC_O ,DAI1_PB04_I);
    SRU2(HIGH,DAI1_PBEN04_I);

    /* PCG clk/fs to SPORT4*/
    SRU2(DAI1_PB05_O  ,SPT4_ACLK_I);
    SRU2(DAI1_PB04_O ,SPT4_AFS_I);

    /*Sport data to DAC data*/
    SRU2(SPT4_AD0_O,DAI1_PB01_I);
    SRU2(HIGH,DAI1_PBEN01_I);

    /*SPDIF Rx*/
    SRU(LOW,DAI0_PBEN09_I);
    SRU(HIGH,DAI0_PBEN03_I);              // RAC_O ---> DAI0_PB09_I ---> DAI0_PB03_I ---> DAI0_PB03_O ---> DAI1_CRS_PB03_O ---> SPDIF_RX_
    SRU(DAI0_PB09_O,DAI0_PB03_I);
    SRU2(DAI1_CRS_PB03_O,SPDIF1_RX_I);

About 0x45

>>> Here 4 denotes that PLL input is from DLR clk
>>>And 5 denotes the Master clock select and Power up the Master

About 0x22

>>> denotes the sample rate frequency is 128/176.4/192 KHz and muted channels

To know more about register settings please refer the ADAU 1962 Datasheet page:25 and 30
www.analog.com/.../ADAU1962.pdf

Also Please refer the Loop filter configurations recommended for DLR clk input in page:13 of ADAU1962 Datasheet

Regards,
Anand Selvaraj.