Dear Team ,
I would modify my query as below :
I am trying to configure a simple passthrough :
ADC -> DSP -> DAC .( All I2S)
Now I am thinking currently to use the PCG to generate clock internally ( from SysClk) to be the clock master for both my ADC and DAC . How do you think ?
What PCG config settings are required to do this ?
Secondly What Register Config on the part of ADC(1979) and DAC(1962) are required to configure them as Slave I2S mode ?
Thirdly will the MCLK be a source of trouble ,if using PCG, currently MCLK pin is connected to DAC .
Will I need SRCs? If yes where exactly?
Also , how about Synchronisation of the PCG clock with SPORT , how do you think ?
We will await some concrete answers on the matters of concern.
[edited by: Hermione at 8:47 PM (GMT -4) on 12 Jul 2022]