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Codec Configuration Registers.

Category: Software
Product Number: NA
Software Version: CCES 2.9.3

Dear Team ,

I would modify my query as below : 

I am trying to configure a simple passthrough : 

ADC -> DSP -> DAC .( All I2S)

Now I am thinking currently to use the PCG to generate clock internally ( from SysClk) to be the clock master for both my ADC and DAC . How do you think ? 

What PCG config settings are required to do this ? 

Secondly What Register Config on the part of ADC(1979) and DAC(1962) are required to configure them as Slave I2S mode ? 

Thirdly will the MCLK be a source of trouble ,if using PCG, currently MCLK pin is connected to DAC .

Will I need SRCs? If yes where exactly?

Also , how about Synchronisation of the PCG clock with SPORT , how do you think ? 

We will await some concrete answers on the matters of concern.





[edited by: Hermione at 8:47 PM (GMT -4) on 12 Jul 2022]
on Jul 12, 2022 2:10 AM in reply to ADIApproved

Dear Anand ,

I am using the 21569



  • FormerMember
    0 FormerMember on Jul 13, 2022 1:04 PM in reply to ADIApproved

    Dear Anand,

    Please reply!

    We are awaiting answers .

  • Hi Hermione,

    For Audio Passthrough in I2S mode, would suggest to refer the example project "Audio_Passthrough_I2S" in BSP of ADSP-2156x which will be useful, you download the BSP using below link.                                                                                                                                                                                                                  After installation : Analog Devices\\ADSP-2156x_EZ-KIT-Rel1.0.1\ADSP-2156x_EZ-KIT\Examples\drivers\adc\Audio_Passthrough_I2S

    As referred in HRM, SYS_CLKIN0 can be used as the input clock for PCG, when configured to use CLKIN as clock source.
    You can refer this in page:1129 in features.                                                                                                             

    Clock can be provided to SPORT either by internal or external(for example from DAC,PCG)

    In BSP example "Audio_Passthrough_I2S", ADAU1962a DAC is configured to provide clock and frame sync to SPORT4A, SPORT4B and ADAU1979 ADC.                                                                                 
    For PCG example, would suggest you the SPDIF example "SPDIF_Loopback" in BSP were PCG A clock provides the Clock for SPORT0A.
    Use this as reference and modify accordingly.
    Path: Analog Devices\\ADSP-2156x_EZ-KIT-Rel1.0.1\ADSP-2156x_EZ-KIT\Examples\drivers\spdif\SPDIF_Loopback.

    Yes, you can use SRCs to synchronize the clocks from different source. About SRC, please refer the BSP example "ASRC_I2S_Mode"                                 
    Path: Analog Devices\\ADSP-2156x_EZ-KIT-Rel1.0.1\ADSP-2156x_EZ-KIT\Examples\drivers\asrc\ASRC_I2S_Mode

    Anand Selvaraj.

  • FormerMember
    0 FormerMember on Jul 19, 2022 9:02 AM in reply to ADIApproved

    Dear Anand ,

    Thank you for the reply.

    My question however still remains .

    Audio_Passthrough_I2S", ADAU1962a DAC is configured to provide clock and frame sync to SPORT4A, SPORT4B and ADAU1979 ADC.                                     

    I don't want DAC to be master .

    I would want PCG to clock both ADC and DAC .

    Would you mind sending me an example code with the Related ADC and DAC settings to do this .



  • FormerMember
    0 FormerMember on Jul 21, 2022 4:31 PM in reply to FormerMember

    Dear Anand !

    Please respond to the query above ...

    I wonder why it takes so long to get a response.

    Is there anywhere else i can look gor some quick answers.

    Please support on this and queries further

  • Hi Hermione

    Apologies for the delay
    Please find the code for Audio passthrough  I2S mode, configuring PCG to provide clock both ADC and DAC .
    Also please note that, If it is a custom board its recommended to use the suggested loop filters (refer: Figure 8) for DLRCLK , which is mentioned under "TYPICAL APPLICATION CIRCUITS" in ADAU1962A Datasheet Page:13. and Figure 15 which is under "PLL AND CLOCK" in ADAU1979 datasheet page:13
    Anand Selvaraj.

  • FormerMember
    0 FormerMember on Jul 22, 2022 10:24 AM in reply to ADIApproved

    Dear Anand

    Thank you that was supportive.

    Meanwhile i am using the EV SOM Board and the problem is that i need to check SPDIF in to Analog Out .

    Can you please share the SRU routing for 2ch SPDIF in to 8 ch DAC out .




  • Hi Hermione,

    Can you refer the Spdif_ASRC_DAC_Passthorugh code from BSP for the SRU connection.              
    In that, the example as Following connections are done using SRU.

    1. SRU(SPDIF0_RX_FS_O,SRC0_FS_IP_I);        // SPDIF0 RX Clock (output) ----> ASRC clock (input)
    2. SRU(SPDIF0_RX_CLK_O,SRC0_CLK_IP_I); // SPDIF0 RX Frame Sync (output) ----> ASRC Frame Sync (input)
    3. SRU(SPDIF0_RX_DAT_O,SRC0_DAT_IP_I);  // SPDIF0 RX Data (output) ----> ASRC Data (input)
    4. SRU(PCG0_FSA_O,SRC0_FS_OP_I);              //  PCG Frame Sync (output) ----> ASRC Frame Sync (output)                                                           
    5. SRU(PCG0_CLKA_O,SRC0_CLK_OP_I);       //  PCG Clock (output) ----> ASRC clock (output)                                                                  
    6. SRU(DAI0_CRS_PB03_O,PCG0_EXTCLKA_I); //  DAI_PIN03 (External clock)(output) ----> PCG Clock Input source (input)
    7. SRU(PCG0_FSA_O,SPT0_BFS_I);                    // PCG Frame Sync (output) ----> SPORT 0B Frame Sync(input)
    8. SRU(PCG0_CLKA_O,SPT0_BCLK_I);             //  PCG Clock (output) ----> SPORT 0B Clock (input)
    9. SRU(SRC0_DAT_OP_O,SPT0_BD0_I);            //   ASRC Data out (output) ----> SPORT0B D0 (input)                                                             
    10. SRU2(PCG0_CRS_CLKA_O ,DAI1_PB05_I);    //  PCG clock (output) ----> DAC clock (DAI1_PIN05)(input)                                                                     
    11. SRU2(PCG0_CRS_FSA_O ,DAI1_PB04_I);       //  PCG Frame Sync (output) ----> DAC Frame Sync (DAI1_PIN04)(input)                                                                
    12. SRU2(DAI1_PB05_O  ,SPT4_ACLK_I);           //  PCG Clock (output) ----> SPORT 4A Clock (input)   
    13. SRU2(DAI1_PB04_O ,SPT4_AFS_I);                //  PCG Frame Sync (output) ----> SPORT 4A Frame Sync(input)
    14. SRU2(SPT4_AD0_O,DAI1_PB01_I);                //  SPORT 4A D0 (output) ----> DAC data (input)
    15. SRU(DAI0_PB09_O,SPDIF0_RX_I);                 //  SPDIF_Rx        
    with this as reference, please modify SRU as per your requirement.   
    If still you are facing issue, please explain your connection with Block diagram. Like how you are going to connect the peripherals.

    Anand Selvaraj.

  • FormerMember
    0 FormerMember on Jul 26, 2022 4:23 AM in reply to ADIApproved

    Dear Anand ,

    In the code you sent me can you cross check the DAC Control 0 and 1 registers ?

    It seems DAC is still programmed as Master?