Change the Core Clock Frequency during Runtime

Hi,

From your query we understand that, you are communicating from controller to target through SPI. In that you want change core clock frequency of target(ADSP-21489) using the commands which is sent by controller . Please correct us if our understanding is wrong.

Regards,
Divya P

That is correct, the ADSP-21489 would be receiving commands to change the Core Clock Frequency. 

Hi Dan,

If you are using VisualDSP please refer the below path to Initialize the PLL configuration commands.
<Installation Path> :\Program Files (x86)\Analog Devices\VisualDSP 5.1.2\214xx\Examples\ADSP-21489 EZ-Board\Power_On_Self_Test\system_init.c

Or if you are using CCES, please refer the example in Board Support Package (BSP). The BSP can be downloaded from the below link.
download.analog.com/.../ADI_ADSP-21489_EZKIT-Rel1.0.0.exe

After installing BSP, please navigate as given below.
<Installation Path> :\Analog Devices\ADSP-21489_EZKIT-Rel1.0.0\21489_EZ-Board\Examples\Power_On_Self_Test\src\system_init.c

Regards,
Anand Selvaraj.

The question was how the Core Clock Frequency can be updated from the SPI or Serial Port at runtime. 

Dan

Hi Dan,

You can try this by using SPI slave boot method. The Host Application would send the Boot Application file (PLL configuration) to the slave via supported protocols (such as SPI) where the slave will receive the .ldr and execute in it's own when it's configured to a boot slave mode by Boot Switch/SYS_BMODE pin.

For changing the PLL configuration please refer the below application note EE-290 which describes how to program the core phase-locked loop (PLL) on ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2148x SHARC® processors.
www.analog.com/.../EE290rev5.pdf

To know about SPI slave boot method please refer "SPI slave Boot Mode" (Pg No: 915) in HRM
www.analog.com/.../ADSP-214xx_hwr_rev1.1.pdf

Regards,
Anand Selvaraj.

Hi Dan,

You can try this by using SPI slave boot method. The Host Application would send the Boot Application file (PLL configuration) to the slave via supported protocols (such as SPI) where the slave will receive the .ldr and execute in it's own when it's configured to a boot slave mode by Boot Switch/SYS_BMODE pin.

For changing the PLL configuration please refer the below application note EE-290 which describes how to program the core phase-locked loop (PLL) on ADSP-2126x, ADSP-2136x, ADSP-2137x, ADSP-2146x, ADSP-2147x and ADSP-2148x SHARC® processors.
www.analog.com/.../EE290rev5.pdf

To know about SPI slave boot method please refer "SPI slave Boot Mode" (Pg No: 915) in HRM
www.analog.com/.../ADSP-214xx_hwr_rev1.1.pdf

Regards,
Anand Selvaraj.