What causes interrupt latency jitter?

Update: I found that the jitter is reduced to 30 ns if I disable a certain lower-priority interrupt that happens at non-periodic intervals. Why would a lower-priority interrupt cause jitter on the interrupt latency of a higher-priority interrupt?

Hi,

Please refer the below threads related to jitter issue. It may be helpful for you.

ez.analog.com/.../adsp21469-timer0-pwm-mode-jitter

ez.analog.com/.../252180

ez.analog.com/.../43346

ez.analog.com/.../294481
 
Regards,
Anand Selvaraj.

Hi Anand - thank you for your response.

The first reference is interesting but also disappointing because the question was not answered by Analog Devices and the user removed the ADSP from his design.

The second reference deals with the latency caused by the dispatcher but not with the jitter - which is the variation of the latency. Is it conceivable that the interrupt dispatcher has execution times that vary as much as 110 ns in increments of 10 ns?

In the third reference the user was happy to report that he reduced the jitter to "only" 100 ns. His finish point is my starting point. I want to know what causes a jitter in this time range? Or precisely: I want to know why disabling a lower priority interrupt reduces it to 30 ns. 

The fourth reference deals with the time taken up by various dispatchers. I am OK with the time taken up by the dispatcher. I don't want any variation thereof. 

Is there some kind of design flaw in the ADSP-21488 that causes interrupt latency jitter even on the highest priority interrupt?

Hi,

Apologies for delayed response.

Were you able to get going.

Please let us know if you are still facing any issue.

Regards,
Anand Selvaraj.

Hi Anand - We're still facing the same issue. I would like to know "What causes this jitter and how can it be reduced?" The references you included in April did not answer this question. 

Hi,

As disabling a lower priority interrupt reduces jitter to 30 ns, we recommend enabling the interrupt nesting option and share the results.
When interrupt nesting is disabled, a higher priority interrupt cannot interrupt a lower priority interrupt’s service routine.
If nesting is enabled and a higher priority interrupt occurs immediately after a lower priority interrupt, the service routine of the lower priority interrupt is delayed.  

The NESTM bit in the MODE1 register directs the processor to enable (if 1) or disable (if 0) interrupt nesting.

If still you are facing issues, can you please share simple project which simulates your jitter issue.
 
Regards,
Divya.P

Hi,

As disabling a lower priority interrupt reduces jitter to 30 ns, we recommend enabling the interrupt nesting option and share the results.
When interrupt nesting is disabled, a higher priority interrupt cannot interrupt a lower priority interrupt’s service routine.
If nesting is enabled and a higher priority interrupt occurs immediately after a lower priority interrupt, the service routine of the lower priority interrupt is delayed.  

The NESTM bit in the MODE1 register directs the processor to enable (if 1) or disable (if 0) interrupt nesting.

If still you are facing issues, can you please share simple project which simulates your jitter issue.
 
Regards,
Divya.P

Hi Divya,

Sorry for the long delay. It appears that the NESTM is set by default on start-up and our code is not modifying it. Therefore all data I shared thus far was already with the NESTM bit set. 

I am running the code on our own hardware which requires a lot of initialization. Reducing the code to a simple project would take some time which I currently cannot invest due to other pressing issues. 

Hi,

 
Please find the attached Timer PWM code for ADSP-21489. It seems that there is no jitters in the signal. Can you please test the code and check whether you are getting any jitter. Please find the image for reference.

Timer_PWM_21489.zip

Regards,
Divya.P