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ADSP-21488 SPI TX Slave Multiple 32bit Values

I have found that when configuring the ADSP-21488 SPI for transmission in slave mode to send multiple 32-bit values (in my case four) that the TXS flag does not behave properly unless the master toggles the chip select after each value. This is the same whether I use DMA to feed the TXSPI or if I "manually" feed the TXSPI during an interrupt.

Is this the normal behavior or is there a way to allow transmission of all four 32-bit values in one transaction?

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  • Hi,

    When the SPI is configured for receive/transmit DMA, the number of words configured in the DMA count register should match the actual data transmitted. When the SPI DMA is used, the internal DMA request is generated for a DMA count of four. In case the count is less than four, one DMA request is generated for all the bytes.

    For example, when a DMA count of 16 is programmed, four DMA requests are generated (that is, four groups of four). For a DMA count of 18, five DMA requests are generated (four groups of four and one group of two). In case the SPI DMA is programmed with a value more than the actual data transmitted, some bytes may not be received by the SPI DMA due to the condition for generating the DMA request.

    Regards,
    Anand Selvaraj.

  • Hi Anand,

    Thank you for your response. I don't believe the issue is with the DMA. It tried both the DMA and the interrupt-driven method with the same result. However, the interrupt-driven method may give better insight into what is going on:

    Using the interrupt-driven method, I get one interrupt immediately when I enable the SPI. So I transfer my first 32-bit value to the TXSPI register. Then I get another interrupt when the master enables the chip select.  So I transfer my second 32-bit value to the TXSPI. After than I don't receive any interrupts anymore even though the master clocks out four 32-bit values. It's as if the TXS never gets cleared even though data is being clocked out of the shift register. As a result the SPI sends the first two values correctly but the third and fourth value are the same as the second. 

    Interestingly the SENDZ bit makes no difference. Even then the third and fourth values are copies of the second value instead of being zero.

    So it appears that the TXS does not "know" how to behave correctly unless the CS is toggled between every 32-bit value. 

    In any case, what would clear this up is if you have a working sample code, where

    1. The ADSP is the slave

    2. The ADSP wants to transmit

    3. There are more than two 32-bit values to be transmitted

Reply
  • Hi Anand,

    Thank you for your response. I don't believe the issue is with the DMA. It tried both the DMA and the interrupt-driven method with the same result. However, the interrupt-driven method may give better insight into what is going on:

    Using the interrupt-driven method, I get one interrupt immediately when I enable the SPI. So I transfer my first 32-bit value to the TXSPI register. Then I get another interrupt when the master enables the chip select.  So I transfer my second 32-bit value to the TXSPI. After than I don't receive any interrupts anymore even though the master clocks out four 32-bit values. It's as if the TXS never gets cleared even though data is being clocked out of the shift register. As a result the SPI sends the first two values correctly but the third and fourth value are the same as the second. 

    Interestingly the SENDZ bit makes no difference. Even then the third and fourth values are copies of the second value instead of being zero.

    So it appears that the TXS does not "know" how to behave correctly unless the CS is toggled between every 32-bit value. 

    In any case, what would clear this up is if you have a working sample code, where

    1. The ADSP is the slave

    2. The ADSP wants to transmit

    3. There are more than two 32-bit values to be transmitted

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