Post Go back to editing



I am using a Sharc 21479 with my own board. I have an application receiving data from an ADC over SPORT (using DMA), processing the data and then streaming the data over SPORT (also with DMA).

The application is working fine but after 1.5 hours the DMA stops working.

After the initialisation the DMA registers look like this:

The DMA is working in chaining mode, so the registers are only written during the initialisation. After the error occured, the DMA registers look like this:

The DMA registers of the SPORT0 have been overwritten. My guess is that a wrong memory access is overwritting the DMA registers.

Is there a possibility to set a breakpoint on these registers. I looked at the hardware breakpoints (I am using VisualDSP) but I did not manage to have it working.

I am not sure how to configure the hardware breakpoint properly:  I/O breakpoint? address: from 0xc00 to 0xc40?

Thanks for your help,


  • Hi,

    1) Are you getting any error or exception?

    2) Can you share the SPORT control and status registers? Can you share the Bclk and FS frequency rate?

    3) What is size of buffer used for receiving ADC data? Is the buffer using internal memory or external memory?

    4) Regarding,"Is there a possibility to set a breakpoint on these registers. I looked at the hardware breakpoints (I am using VisualDSP) but I did not manage to have it working."
    >> If the registers are used in user code, we can place the break point at the particular line and check the register value in register window once step-in is pressed.
    >> We suggest to refer the below FAQ at

    Anand Selvaraj.

  • Hello Anand,


    Thanks for your answer.

    Below my answer to your questions:


    1. I am streaming audio data, so I can hear when an error occurred: the sound becomes horrible… I could then see with the debugger that I had an SPORT error and the DMA error mentioned previously.

    After initialisation:



    After error:



    2. I am sensing you the original code for the SPORT:



    I am also sending you a simplified version of the main thread:



    I could find out that the DMA error occurs before the SPORT error.


    I am sampling and streaming the data with 48kHz. The core clock is running at 256 MHz and the SDRAM clock at 128MHz. I am not sure what you mean with Bclk…

     3. The DMA Buffer size is 960. And both the receiving and the transmitting buffer are in the external memory (SDRAM).


    4. I can normally use breakpoints. In this case, I don’t know where to put the breakpoint as the IISP0 register is not written directly in my code. For this reason I wanted to use an hardware breakpoint on this register. I tried the configuration below but it did not worked. Do you see any error?



    Thanks and regards,


  • Hello Anand,

    yesterday I moved the TX buffer from external to internal memory.

    It looks like the problem disappeared. My application is now running since 3 hours without errors.

    I was having around 1.000.000 read/write accesses to the SDRAM per second, with the SDRAM running at 128MHz. I did not optimise anything about the memory management, how/where the data are saved...

    Do you think it could be a congestion problem to access to the SDRAM?  Can this explain the DMA error I had?

    Thanks for your help,


  • Hi,

    1) Are you using any other SPORT's other than SPORT0 and SPORT1?

    2) We suggest to refer 15000018 - SPORT DMA Failures when Grouped SPORTs Target Both Internal and External Memory: anomalies from below link
    Anand Selvaraj.

  • Hallo Anand,

    I am only using SPORT0 and SPORT1.

    I have now moved the TX/RX Buffer to the external memory as well as the TCB as described in the workaround. My application is running since 4 hours without errors.

    I will do more extending tests next week.

    Thanks for your help.



Reply Children
No Data