How to configure ADAU1966A for 16-channel TDM DAC via SPI using 21489?

I want to configure the ADAU1966A for 16-channel TDM mode DAC via SPI. i configure the register values as shown in Figure 1.Am I configuring this wrong? Thanks for the answer.

And how do I configure 16 channels of TDM in SPORT? How should I write the TCB? I am referring to the routine AD1938, hope to get help! Thank you guys!

The code is as follows:

unsigned int PCI = 0x00080000 ;
unsigned int OFFSET = 0x00080000 ;

// SPORT RX DMA destination buffers
section("seg_dmda") int RxBlock_A0[NUM_SAMPLES*NUM_RX_SLOTS];
section("seg_dmda") int RxBlock_A1[sizeof(RxBlock_A0)];

// SPORT Tx DMA source buffers NUM_TX_SLOTS = 16
section("seg_dmda") int TxBlock_A0[NUM_SAMPLES*NUM_TX_SLOTS];
section("seg_dmda") int TxBlock_A1[sizeof(TxBlock_A0)];

// TCB blocks for Chaining
// Each block will be used for:
//      Filling from the ADC
//      Processing filled data

//Set up the TCBs to rotate automatically
int TCB_RxBlock_A0[4] = { 0, sizeof(RxBlock_A0), 1, 0};
int TCB_RxBlock_A1[4] = { 0, sizeof(RxBlock_A0), 1, 0};

int TCB_TxBlock_A0[4] = { 0, sizeof(TxBlock_A0), 1, 0};
int TCB_TxBlock_A1[4] = { 0, sizeof(TxBlock_A0), 1, 0};

void InitSPORT()
{

// Set up "ping-pong" chained DMAs for AD1939-ADAU1966A
    //Proceed from Block A0 to Block A1
    TCB_RxBlock_A0[0] = (unsigned int) TCB_RxBlock_A1 + 3 - OFFSET + PCI ;
    TCB_RxBlock_A0[3] = (int) RxBlock_A0 - OFFSET ;

    //Proceed from Block A0 to Block A1
    TCB_TxBlock_A0[0] = (unsigned int) TCB_TxBlock_A1 + 3 - OFFSET ;
    TCB_TxBlock_A0[3] = (int) TxBlock_A0 - OFFSET ;

    //Proceed from Block A1 to Block A0
    TCB_RxBlock_A1[0] = (unsigned int) TCB_RxBlock_A0 + 3 - OFFSET + PCI ;
    TCB_RxBlock_A1[3] = (int) RxBlock_A1 - OFFSET ;

    //Proceed from Block A1 to Block A0
    TCB_TxBlock_A1[0] = (unsigned int) TCB_TxBlock_A0 + 3 - OFFSET ;
    TCB_TxBlock_A1[3] = (int) TxBlock_A1 - OFFSET ;

    
    //Clear out SPORT 0/1 registers
	*pSPMCTL0 = 0;
	*pSPMCTL1 = 0;
    *pSPCTL0 = 0;
    *pSPCTL1 = 0;

    /////////////////////////////////////////////////////////////////////////////////////
    //      Analog Input and output setup
    /////////////////////////////////////////////////////////////////////////////////////
    
    // External clock and frame syncs generated by AD1939
   	*pDIV0 = 0x00000000;  // Transmitter (SPORT0)
    *pDIV1 = 0x00000000;  // Receiver (SPORT1) at 12.288 MHz SCLK and 48 kHz sample rate
    
    // Configuring SPORT0 & SPORT1 for "Multichannel" mode
	// This is synonymous with TDM mode which is the operating mode for the AD1939 */
	
	// Enabling DMA Chaining for SPORT0 TX/SPORT1 RX
    // Block 1 will be filled first
    
    *pCPSP0A = (unsigned int)TCB_TxBlock_A0 - OFFSET + 3 + PCI;
    
    *pCPSP1A = (unsigned int)TCB_RxBlock_A0 - OFFSET + 3 + PCI;
	
	// sport1 control register set up as a receiver in MCM
	// sport 1 control register SPCTL1 = 0x000C01F0 
	// externally generated SCLK1 and RFS1 
	*pSPCTL1 = 	SCHEN_A | SDEN_A | SLEN32; 
	// SCHEN_A :SPORT TXnA/RXnA 
	//SDEN_A :SPORT TXnA/RXnA 
	//SLEN32 :32
	
	// sport0 control register set up as a transmitter in MCM
	// sport 0 control register, SPCTL0 = 0x000C01F0
	*pSPCTL0 = 	SCHEN_A | SDEN_A | SPTRAN | SLEN32;

	// sport1 receive & sport0 transmit multichannel word enable registers 
//    *pSP1CS0 = 0x0000000F;	// Set to receive on channel 0-3 on SPORT1->1111
//    *pSP0CS0 = 0x000000FF;	// Set to transmit on channel 0-7 on SPORT0->1111 1111

    *pSP1CS0 = 0x0000000F;	// Set to receive on channel 0-3 on SPORT1->1111
    *pSP0CS0 = 0x0000FFFF;	// Set to transmit on channel 0-15 on SPORT0->1111 1111 1111 1111


	// sport1 & sport0 receive & transmit multichannel companding enable registers 
	// no companding for our 4 RX and 16 TX active timeslots
	// no companding on SPORT1 receive 
	// no companding on SPORT0 transmit 
	*pMR1CCS0 = *pMT0CCS0 = 0;

	// SPORT 0&1  Miscellaneous Control Bits Registers 
	// SP01MCTL = 0x000000E2,  Hold off on MCM enable, and number of TDM slots to 8 active channels
	// Multichannel Frame Delay=1, Number of Channels = 15, LB disabled 
	*pSPMCTL0 = NCH15 | MFD1;
	*pSPMCTL1 = NCH7 | MFD1;

    
    
	// Enable multichannel operation (SPORT mode and DMA in standby and ready)
	*pSPMCTL0 |= MCEA;
	*pSPMCTL1 |= MCEA;
}