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How do I setup my project to use available memory correct?

How do I setup my project to use available memory correct?

How does each core in my project know how to use L3 DDR3 memory (how do I partition the L3 memory for each core)?

How do I partition the on chip L2 SRAM between the cores?

How do I set the L3 DDR3 clock frequency?

How do I setup a shared memory that all cores can access (in L2 or L3)?

is there any tutorial (all this is new to me)?

Found an answer for how do I set the L3 DDR3 clock frequency
[edited by: masip at 12:47 PM (GMT -4) on 20 Apr 2021]
  • I found where to setup the DCLK for the DDR3 in sc5xx_init.h:


    Is it ok to adjust this for a lower frequency or do I need to change something else?

    The reason for this question is that we may plan to use an FPGA connected to the DDR3 bus to memory map registers on specific addresses. And then we would probably need to decrease the DCLK so the FPGA can handle the speed.

  • Hi,

    Yes, your understanding is correct. As mentioned in the "readme.txt" of an appropriate initcode project, By default, the project will use CGU0 to set the core and DDR clocks to the maximum possible on most EZ-KITs, being either 400MHz or 450MHz. It is possible to override the Core and DDR clock speeds by modifying the macros CONFIG_CORE_CLOCK_SPEED and CONFIG_DDR_CLOCK_SPEED in config.h to the required frequency.

    In order to configure the DDR, please refer the Clock Generation Unit (CGU) (Page No: 3–1 (152 / 3973)) section in the ADSP-SC5xx HRM manual. We suggest you to refer the "Clock Operating Conditions" in the datasheet and please make sure that the Clock Operating conditions doesn't exceeds.
    Anand Selvaraj