Best practice to interfacing SC573 to FPGA. Best interface to use (LP, EPPI or DDD3 memory mapping)?

We would like to interface an SC573 to an FPGA to be able to read multiple registers from the FPGA and also write to multiple registers in the FPGA. Previous design (different DSP) has used memory mapped FPGA registers.

What is best practice on the SC573?

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  • +1
    •  Analog Employees 
    on Apr 21, 2021 5:53 AM

    Hi,

    Unfortunately, SMC is not supported in ADSP-SC573 processors. Hence there is no way to connect gluelessly any SRAM or FPGA with asynchronous bus interface.

    EPPI can support direct connections to active TFT LCDs, parallel A/D and D/A converters,video encoders and decoders, image sensor modules and other general-purpose peripherals.

    Link ports allow the processor to connect to other processors or peripheral link ports using a simple communication protocol for high-speed parallel data transfer. This peripheral allows various I/O peripheral interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessing schemes.

    Link ports can operate independently and simultaneously, allowing glueless high-speed connectivity of up to four external processors

    For more information, please refer ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference manual linked below:
    www.analog.com/.../adsp-sc57x-2157x_hwr.pdf

    Regards,
    Anand Selvaraj.

Reply
  • +1
    •  Analog Employees 
    on Apr 21, 2021 5:53 AM

    Hi,

    Unfortunately, SMC is not supported in ADSP-SC573 processors. Hence there is no way to connect gluelessly any SRAM or FPGA with asynchronous bus interface.

    EPPI can support direct connections to active TFT LCDs, parallel A/D and D/A converters,video encoders and decoders, image sensor modules and other general-purpose peripherals.

    Link ports allow the processor to connect to other processors or peripheral link ports using a simple communication protocol for high-speed parallel data transfer. This peripheral allows various I/O peripheral interconnection schemes to I/O peripheral devices as well as co-processing and multiprocessing schemes.

    Link ports can operate independently and simultaneously, allowing glueless high-speed connectivity of up to four external processors

    For more information, please refer ADSP-SC57x/ADSP-2157x SHARC+ Processor Hardware Reference manual linked below:
    www.analog.com/.../adsp-sc57x-2157x_hwr.pdf

    Regards,
    Anand Selvaraj.

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