I do MDMA with an ADSP-SC589 on two channels, once with DMA8/DMA9 once with DMA18/DMA19 both transferring data from SHARC+ core1 L1 memory to L2 system memory.
As the DMA transfer ist register base the start trigger is given by a write to the Config register of the apropriate MDMA channels.
I configure the SPU accordingly and use the system memory map to access SHARC+ L1 memory width the DMA channel. Interrupts for IRQerr and IRQdone are installed and active.
After system start I see both MDMA working for a short while. Then, DMA18/DMA19 stops transferring data, investigating the STAT register of the destination channel DMA19 showing a run status that is still 2, which means DATA TRANSFER, while the source channel's STAT register DMA18 indicates a RUN status of 0 (STOP/IDLE --> completed).
Do you have any clue how I can prevent a stall like that?
Hi,Can you please share the MDMA configurations? It would be helpful if you can share a minimal project to replicate the issue at my end. Meanwhile, can you also check if DMA8/DMA9 and DMA18/DMA19 are properly working separately?Regards,Anand Selvaraj.
Do we have a solution for the above stalling issue. I observed similar behavior. I am using MDMA 39 and 40 to transfer data between L1 and L3 memory location. I setup DMA destination interrupt DMA 40. But i can see its keep on getting MDMA interrupt. DMA status register of MDMA 39 is showing RUN state as '2' while DMA 40 is '0'. Is this an issue with ADI driver code ?
Hi Varun,It would be helpful if you can share the MDMA configurations? If possible, share a minimal project to replicate the issue at my end. Regards,Anand Selvaraj.