I do not know the SHARC programming details. I support the AD1939 so I can inform you about some of the requirements of the codec.
For a 16kHz sampling rate you must supply the codec with a master clock that is 512 times the sampling rate. That would be 8.192MHz master clock frequency. I think on this evaluation board it is a crystal that is supplying the master clock? So you may have to change the crystal.
At this sample rate you actually have two choices. The minimum frequency of the PLL is 6.9MHz so the 8.192 is within this specification but you will need to set the PLL into the 512 x fs mode. If the source is a crystal then the jitter will be good so it is probably best to not use the PLL and just direct clock the ADC and the DAC. Fortunately, these are just register settings for both options.
In the PLL and Clock Control Register 0, bits 2:1, you will find the Master Clock Rate Setting. Set these bits to 0b10 which is the 512xfs setting if you want to use the PLL. The rest of the sampling rate settings will remain the same. In the defines they will probably be listed as 48kHz so that is the correct setting.
If you want to direct clock the part. Then in the PLL and Clock Control Register 1 you will find bit 0 and bit 1 are for selecting the DAC and ADC clock sources. Set these to MCLK instead of PLL clock and then it will be getting its clock directly from the MCLKIN pin.
Again. All the other settings should be fine as they are, the default is set to 48kHz fs. With the lower master clock frequency the actual sample rate will be 16kHz.
Hopefully, someone else on the SHARC team will chime in with some of the details of this eval board and using the defines properly.
In order to use the AD193x at these lower sample rates, an MCLK of 512 x Fs must be provided at the MCLKI port.
The MCLK oscillator would need to be changed to 8.192MHz. Just make sure that the MCLK is correlated with the LRCLK and BCLK. This mode is called Direct Clocking. The Fs is divided down directly from the MCLK frequency. The BCLK frequency remains 64 x Fs.
In order to use the AD193x at these lower sample rates, an MCLK of 512 x Fs must be provided at the MCLKI port.
The MCLK oscillator would need to be changed to 8.192MHz. Just make sure that the MCLK is correlated with the LRCLK and BCLK. This mode is called Direct Clocking. The Fs is divided down directly from the MCLK frequency. The BCLK frequency remains 64 x Fs.
