I am using the ADZS-SC589-EZLITE and the basic signal flow of my program is given below:
audio from SPDIF @ 48khz -> upsampling filter to 192khz -> DAC @ 192kHz.
The function of the program requires that no ASRCs are present in the signal flow as it must remain bit perfect from input to DAC, but the documentation for the onboard Precision Clock Generators doesn't seem to mention any clock multiplier within them.
How should i set up the clocks so that the DAC frame and bit clock are running synchronously with the SPDIF clocks but with the DAC clocks being a 4x multiple of the SPDIF clocks?
The PCGs only divide and the recovered clock will be too low.
You would need to add an external PLL. With a fractional N PLL you can multiply the recovered clock with about 50ps of jitter which is probably much better than the incoming S/PDIF. You can do much better in this respect with a good local clock and the ASRC