ADSP-21489 LFS - Active Low Frame Sync

Hi,

The ADC I am using has an active low frame sync, when I configure the ADSP-21489 SPORT SPCTL1 register and set the LFS bit(Active Low Frame Sync) to a 1 the DSP reads zeros 99 percent of the time. If I set the LFS to a zero which should be Active High Frame Sync and incorrect the DSP reads correctly. The LFS bit operates the opposite from the documentation.

Polarity Level Frame Sync. This bit selects the logic level of the
(transmit or receive) frame sync signals for standard and multichan
nel modes if the FSED bit in SPCTLNx register is cleared (=0).
0 = Active high frame sync
1 = Active low frame sync

What am I missing?

Thanks

Dan

The output of the AD7768 is shown below.

Relevant code; 

static void timer_isr(uint32_t iid, void* handlerArg)

   {
      volatile int *timer_counter = (int *) handlerArg;
      *timer_counter += 1;
   }

static void sport1_isr(uint32_t iid, void* handlerArg)
{
	volatile int *sport1_counter = (int *) handlerArg;
	*sport1_counter += 1;

	adcCode1 = *pRXSP1B;
    dataReady = true;
}

int main(int argc, char *argv[])
{
 	adi_initComponents();
	*pPICR2 &= ~(0x3E0); //Sets the UART0 receive interrupt to P13
	*pPICR2 |= (0x13<<5);
	initPLL();
	initExternalMemory();

	InitSPORT1();

	adi_int_InstallHandler(ADI_CID_TMZHI, //iid - high priority core timer
					               timer_isr,    // handler
								   (void *)&timer_isr_count1, //handler parameter
					                true           //do enable
);

	adi_int_InstallHandler(ADI_CID_P3I, //Programmable Interrupt 3 - SPORT1
						               sport1_isr,    // handler
									   (void *)&sport1_isr_count, //handler parameter
						                true           //do enable
);

	timer_set (449994,449994);  // set tperiod and tcount of the timer 1mS interrupt with 449.994600 MHz CC
	timer_on () ;  // start timer

	for (rx_count = 0; rx_count < 1955; rx_count++)
	{
	while (!dataReady){}
	adcCode1 = adcCode1 & 0x00FFFFFF;

	if (adcCode1 & 0x800000){
			outputCodeChan1[rx_count] = adcCode1 |= 0xFF000000L;
	}	else{outputCodeChan1[rx_count] = adcCode1;}

	adcChan1[rx_count] = (outputCodeChan1[rx_count] * .0000004883);

	dataReady = false;

	}
	timer_off () ;  // stop timer
	return 0;
}

void InitSPORT1(void)
{
	//*pSPCTL1 = 0;
	//*pDIV1 = 0;

	//SPTRAN = SPORT data buffer data direction '1' = transmitter, '0' = receiver
	//SPEN_B = Serial port B channel enabled
	//IFS = 0 external frame sync
	//FSR = 1 Frame sync (FSx) required
	//CKRE = 0 processor selects the falling edge of SPORTx_CLK
	//OPMODE = 0 DSP standard /multichannel mode
	//ICLK = 0 Select external transmit clock
	//SLEN32 = 33 SLEN32 (serial word length–1)
	//LFS = 1 Frame Sync active low
	//SPEN_A = Serial port A channel enabled
	
	*pSPCTL1 = SPTRAN|SPEN_B|IFS|FSR|CKRE|OPMODE|ICLK|SLEN32|LFS;
}