Say I have this requirement: 24.576MHz master clock, generate 192K stereo audio (bit clock = 2 * 32 * 192000 = 12.288MHz)
So I can use PCG to divide the master clock by 2, then further divide by 64 for the word clock and phase shift the word clock by 1 to align it with the bit clock falling edge.
Now if I want to generate 384K stereo audio (bit clock = 2 * 32 * 384000 = 24.576MHz.
Set the PCG to divide by 1 for the bit clock, then further divide by 64 for the word clock. But I can't phase shift the word clock by 1/2 to align it with the bit clock falling edge.
So when the bit clock divider is 1, how to use PCG to generate compliant I2S word clock?
Hi,Could you please let me know which processor are using?.However I would suggest the below points,Phase shift is a frame sync parameter that defines the phase shift of the frame sync with respect to the input clock of the same unit. This feature allows shifting of the frame sync signal in time relative to the clock input signal. Frame sync phase shifting is often required by peripherals that need a frame sync signal to lead or lag a clock signal.For example, the I2S protocol specifies that the frame sync transition from high to low occur one clock cycle before the beginning of a frame. Since an I2S frame is 64 clock cycles long, delaying the frame sync by 63 cycles produces the required framing.Please refer the Phase shift section (PageNo:702 / 1304)in the HRM of ADSP 214xx. You can find the HRM from below link. It explain shifting of the frame sync signal in time relative to the clock input signal.www.analog.com/.../ADSP-214xx_hwr_rev1.1.pdfRegards,Lalitha.S
Processor: ADSP-21584The PCG's appear to be always clocked on rising edge of clock. I2S Tx requires data and word clock changing on -ve edge of bit clock.
If the bit clock divisor is set to 1, how to generate I2S output with data and frame sync changing on -ve edge of bit clock? (if the divisor is e.g. 2, I can set phase shift to 1 and that aligns the data and frame sync to bit clock -ve edge)
Hi,Please note that,If the phase shift is 0 (see the Phase and Pulse Width Settings figure), the clock and frame sync outputs rise at the same time. If the phase shift is 1, the frame sync output transitions one input clock period ahead of the clock transition. If the phase shift is divisor – 1, the frame sync transitions divisor – 1 input clock periods ahead of the clock transitions. When generating single frame sync pulses (the length of one SPORT clock cycle), take care with respect to the drive and sampling edges. If the rules are violated, for example if the SPORT is not driving data, the module cannot detect a valid sample edge.
"Please note that,If the phase shift is 0 (see the Phase and Pulse Width Settings figure), the clock and frame sync outputs rise at the same time"
Indeed. Not compliant with I2S. So there is no workaround to make this compatible with I2S? (if we redid the hardware, I would add an external inverter to the I2S clock).
Hi,The above information which I have shared is for ADSP-214xx. Please refer the SPORT(PageNo:2664 / 3973) related informations in the ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference Manual.
You can refer the HRM from below link,www.analog.com/.../SC58x-2158x-hrm.pdfRegards,Lalitha S