PCG and I2S compliance when external clock = bit clock

Say I have this requirement: 24.576MHz master clock, generate 192K stereo audio (bit clock = 2 * 32 * 192000 = 12.288MHz)

So I can use PCG to divide the master clock by 2, then further divide by 64 for the word clock and phase shift the word clock by 1 to align it with the bit clock falling edge.

Now if I want to generate 384K stereo audio (bit clock = 2 * 32 * 384000 = 24.576MHz.

Set the PCG to divide by 1 for the bit clock, then further divide by 64 for the word clock. But I can't phase shift the word clock by 1/2 to align it with the bit clock falling edge.

So when the bit clock divider is 1, how to use PCG to generate compliant I2S word clock?