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ADSP-21479 PCG CLK inversion

jb@hme
on Aug 7, 2018

The ADSP-21479 Processor Hardware Reference Manual Figure 15-1 "PCG Block Diagram" on page 15-6 shows that the PCG CLK can be inverted (see attached), but I can’t seem to find how to do that described anywhere in the manual. I don't even understand how the inverter placed in parallel with the CLKDIV block is supposed to work for CLKDIV > 1.  Is it trying to say that inversion of the clock output is only supported in BYPASS mode?

  • 0
    •  Analog Employees 
    on Aug 15, 2018 4:02 AM
    Hi Jb,
    All though figure 15-1 is illustrates the inverse of CLKIN (SERIAL CLOCK), it seems to be a document error.Phase shift is a frame sync parameter that defines the phase shift of the frame sync with respect to the input clock of the same unit. This feature allows shifting of the frame sync signal in time relative to the clock input signal.Please note that phase shifting is specified as FSxPHASE_HI bit field (bits 29–20) of the a 2 x 10-bit divider value in the PCG_CTLxO register and in the FSxPHASE_LO bit field (bits 29–20) of the PCG_CTLx1 register.Other way is to invert your clock signal is to route them to DAI_PB19 or DAI_PB20 pin, which has the pin invert feature. It can be enabled using SRU_PIN3 register.
    Best Regards,
    Jithul
  • 0 on Aug 15, 2018 10:45 PM

    I ended up doing the latter (routing my signal to DAI_PB19 and using its pin invert feature). Thanks for clarifying.