The ADSP-21479 Processor Hardware Reference Manual Figure 15-1 "PCG Block Diagram" on page 15-6 shows that the PCG CLK can be inverted (see attached), but I can’t seem to find how to do that described anywhere in the manual. I don't even understand how the inverter placed in parallel with the CLKDIV block is supposed to work for CLKDIV > 1. Is it trying to say that inversion of the clock output is only supported in BYPASS mode?