SHARC Processors

Q&A

by DMoog
SHARC Processors

Latest 7 days ago by NandiniC
64 1 0
Not Answered
Interfacing external ADC with ADSP-21569 using DAI and SRU. 0
Not Answered

Hello, for my application I need to interface an external ADC with ADSP-21569. I am using the ADSP-21569 SOM with SOMCRR-EZLITE board. I wish to communicate between the ADC and DSP using I2S, with DSP acting as target and ADC acting as controller(generates...

ADSP-21569 Datasheet/Specs sru dai processors and dsp Processors and Microcontrollers sport Show More

64 1 0
by InoJosh
SHARC Processors

Latest 26 days ago by NandiniC
292 5 0
Answered
SHARC-FX: nested interrupts 0
Answered

I have been porting a working application from ADSP-21569 (SHARC+) to ADSP-21834 (SHARC-FX). I made all the necessary changes in order to get it to compile. As far as running the application, I have hit a roadblock related to nested interrupts. I...

Audio Signal Processors ADSP-21834 hardware SHARC-FX SHARC Audio Processors/SoCs Show More

292 5 0
by dspPro
SHARC Processors

Latest 1 month ago by NandiniC
177 1 0
Answered
SPORT Syncing Problem 0
Answered

We are currently working on a project where the SHARC ADSP21489 does the job of a distributor on an audio platform. It receives tdm8 from a audio host with 48khz and can send back tdm8 to the host. Further, it should play audio with 192khz over i2s. This...

software sharc adsp-21489 audio-processing processors and dsp Processors and Microcontrollers Show More

177 1 0
by athapa
SHARC Processors

Latest 2 months ago by NandiniC
200 3 0
Not Answered
FFT/FIR accelerator alternating between FFT and FIR mode at 18kHz 0
Not Answered

Hello, I have a requirement where I need am using the FIR accelerator for as a filter. I also need to perform FFT 'simultaneoulsy'. Since the FFT/FIR accelerator can only perform any one function at a time, would it be feasible to have it alternate...

hardware fft accelerator fir accelerator adsp21489

200 3 0
by MichaelF91
SHARC Processors

Latest 2 months ago by MichaelF91
253 3 0
Answered
Is configuring IIR accelerator DMA burst mode supported when using the driver functions in CCES? 0
Answered

Reading the hardware reference manual, it says that there is a control bit (IIR_CTL1.BURSTEN) which enables INCR8 DMA burst mode. I wanted to use this feature, but I'm using the driver functions in CCES (adi_iir_Open(), etc), and I can't see anywhere...

Audio Signal Processors hardware ADSP-21565 iir accelerator SHARC Audio Processors/SoCs Show More

253 3 0
by JohnG2024
SHARC Processors

Latest 2 months ago by JohnG2024
469 6 0
Answered
Is there a optimized Q1_23 to float function thats faster than the conv_RtoF() builtin function for SHARC+ 0
Answered

I am wondering if there is a faster way to convert integer to float if it is known to be Q1.24 format numbers, as compared to the builtin_conv_RtoF which handles 32 bits input ?

Audio Signal Processors software SHARC Audio Processors/SoCs adsp-21593

469 6 0
by cristiano
SHARC Processors

Latest 2 months ago by cristiano
282 2 0
Not Answered
Is there any reference design for interfacing Linux with Sharc cores? 0
Not Answered

Hi all I have a SC598-SOM + EV-SOMCRR evaluation kit and I want to build a system which it's supposed to work this way: - Linux running on ARM core which takes care of network interface via the 1Gb ethernet port (EMAC0) - Custom bare-metal code running...

Audio Signal Processors SC59x hardware peripherals adsp-sc598 linux SHARC Audio Processors/SoCs Show More

282 2 0
by Shark111
SHARC Processors

Latest 3 months ago by Santhakumari
730 9 0
Answered
Converting VisualDSP++ project to CCES project 0
Answered

I have a VisualDSP++ (Version 5.1.2.0) project written in assembly for part ADSP-21489. We recently switched to CrossCore Embedded Studio V2.12.1.0, and used t he Project Import Wizard to convert the VisualDSP++ project to CCES project, which was compiled...

Audio Signal Processors software adsp-21489 VDSP++ V5.1.2.0 CCES V2.12.1.0 SHARC Audio Processors/SoCs Show More

730 9 0
by Mike33
SHARC Processors

Latest 4 months ago by Mike33
215 2 0
Answered
MDMA Stall 0
Answered

Hi team, I am trying to excute mdma from L1 memory to SMC interface which is connected to FPGA. In my test code mdma works fine, but in the target program mdma stalls. Registers right after mdma requested: DMA8: CFG 04000201 STAT 00006000 AddrStart...

Audio Signal Processors hardware SHARC Audio Processors/SoCs ADSP-21587 mdma Show More

215 2 0
by ssirri
SHARC Processors

Latest 5 months ago by NandiniC
165 1 0
Answered
Datasheets give conflicting specifications about temperature range +1
Answered

Hello I was looking for ADSP-21489BSWZ-4B DSP for one of my projects but I encounter conflicting information in datasheets of products. In the datasheet dated 2012 this product is listed as -40 to +85 degrees celcius, however in the datasheet dated...

Audio Signal Processors Datasheet/Specs adsp-21489 ADSP-21489BSWZ-4B adsp21489 21489 SHARC Audio Processors/SoCs Show More

165 1 0
by hiro.sp
SHARC Processors

Latest 5 months ago by NandiniC
178 3 0
Suggested Answer
SC589_EZ-BOARD uses DDR3 with series termination, Why? 0
Suggested Answer

I'm confused. SC589_EZ-BOARD uses DDR3 with series termination, so why is the VTT termination method not used? Also, the technical note EE-387 does not mention VTT termination at all. Previously, I was using DDR3 with the SC584, which used series...

ddr3 hardware sharc dmc adsp-sc589 Processors & Microcontrollers Processors and Microcontrollers Heterogeneous Multicore Processors Show More

178 3 0
by EricSa
SHARC Processors

Latest 5 months ago by NandiniC
267 2 0
Not Answered
SPORT primary and secondary on EV-SOMCRR-EZLITE +1
Not Answered

Hey together, we have the ADSP-21569 SOM with the EV-SOMCRR-EZLITE and we want to understand the SPORT handling more in detail. So far we are able to run the example code for the ADAU1372 and receive and transmit 2 channels from and to the mini jacks...

ADSP-21569 Audio Signal Processors software CCES 2.12.1 SHARC Audio Processors/SoCs Audio CODECs Show More

267 2 0
by MichaelF91
SHARC Processors

Latest 6 months ago by NandiniC
222 2 0
Answered
Understanding adi_spdif_Rx_EnableAutoAudioRestart 0
Answered

The hardware reference manual on p. 1257 states the following: Interrupted Data Streams on the Receiver When using the S/PDIF receiver with data streams that are likely to be interrupted, (in other words unplugged and reconnected), it is necessary to...

software ADSP21565

222 2 0
by MichaelF91
SHARC Processors

Latest 6 months ago by NandiniC
155 1 0
Answered
Is there a disadvantage to setting SPDIF_RX_CTL.FASTLOCK to 1? 0
Answered

The manual states that enabling fast mode has the "advantage of recovering very quickly whenever the S/PDIF receiver looses lock due to glitches in the signal". What is the disadvantage, or, to phrase it another way, is there ever any reason not to...

Audio Signal Processors software ADSP-21565 SHARC Audio Processors/SoCs

155 1 0
by LeopoldoBudde
SHARC Processors

Latest 7 months ago by LeopoldoBudde
452 2 0
Not Answered
Tx SPORT DMA interruption unaligned with respect to Rx despite same LRCLK and BCLK signals and configs in SHARC-FX ADSP-SC835 +2
Not Answered

Hello, I am working with ADSP-SC835 (SOM + SOMCRR board) and CCES 3.0.2. I have a simple scheme where I receive external LRCLK and BCLK signals, working in TDM4 (multichannel) mode, where SPORT5A receives the input data on both data lines (D0 and D1)...

hardware dma SHARC-FX tdm sport cces-3.0.2 ADSP-SC835 Show More

452 2 0

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Q&A

Not Answered
Interfacing external ADC with ADSP-21569 using DAI and SRU. 0
Not Answered

Answered
SHARC-FX: nested interrupts 0
Answered

Answered
SPORT Syncing Problem 0
Answered

Not Answered
FFT/FIR accelerator alternating between FFT and FIR mode at 18kHz 0
Not Answered

Answered
Is configuring IIR accelerator DMA burst mode supported when using the driver functions in CCES? 0
Answered

Answered
Is there a optimized Q1_23 to float function thats faster than the conv_RtoF() builtin function for SHARC+ 0
Answered

Not Answered
Is there any reference design for interfacing Linux with Sharc cores? 0
Not Answered

Answered
Converting VisualDSP++ project to CCES project 0
Answered

Answered
MDMA Stall 0
Answered

Answered
Datasheets give conflicting specifications about temperature range +1
Answered

Suggested Answer
SC589_EZ-BOARD uses DDR3 with series termination, Why? 0
Suggested Answer

Not Answered
SPORT primary and secondary on EV-SOMCRR-EZLITE +1
Not Answered

Answered
Understanding adi_spdif_Rx_EnableAutoAudioRestart 0
Answered

Answered
Is there a disadvantage to setting SPDIF_RX_CTL.FASTLOCK to 1? 0
Answered

Not Answered
Tx SPORT DMA interruption unaligned with respect to Rx despite same LRCLK and BCLK signals and configs in SHARC-FX ADSP-SC835 +2
Not Answered

Q&A

Not Answered Interfacing external ADC with ADSP-21569 using DAI and SRU. 0 Not Answered

Answered SHARC-FX: nested interrupts 0 Answered

Answered SPORT Syncing Problem 0 Answered

Not Answered FFT/FIR accelerator alternating between FFT and FIR mode at 18kHz 0 Not Answered

Answered Is configuring IIR accelerator DMA burst mode supported when using the driver functions in CCES? 0 Answered

Answered Is there a optimized Q1_23 to float function thats faster than the conv_RtoF() builtin function for SHARC+ 0 Answered

Not Answered Is there any reference design for interfacing Linux with Sharc cores? 0 Not Answered

Answered Converting VisualDSP++ project to CCES project 0 Answered

Answered MDMA Stall 0 Answered

Answered Datasheets give conflicting specifications about temperature range +1 Answered

Suggested Answer SC589_EZ-BOARD uses DDR3 with series termination, Why? 0 Suggested Answer

Not Answered SPORT primary and secondary on EV-SOMCRR-EZLITE +1 Not Answered

Answered Understanding adi_spdif_Rx_EnableAutoAudioRestart 0 Answered

Answered Is there a disadvantage to setting SPDIF_RX_CTL.FASTLOCK to 1? 0 Answered

Not Answered Tx SPORT DMA interruption unaligned with respect to Rx despite same LRCLK and BCLK signals and configs in SHARC-FX ADSP-SC835 +2 Not Answered

Not Answered
Interfacing external ADC with ADSP-21569 using DAI and SRU. 0
Not Answered

Answered
SHARC-FX: nested interrupts 0
Answered

Answered
SPORT Syncing Problem 0
Answered

Not Answered
FFT/FIR accelerator alternating between FFT and FIR mode at 18kHz 0
Not Answered

Answered
Is configuring IIR accelerator DMA burst mode supported when using the driver functions in CCES? 0
Answered

Answered
Is there a optimized Q1_23 to float function thats faster than the conv_RtoF() builtin function for SHARC+ 0
Answered

Not Answered
Is there any reference design for interfacing Linux with Sharc cores? 0
Not Answered

Answered
Converting VisualDSP++ project to CCES project 0
Answered

Answered
MDMA Stall 0
Answered

Answered
Datasheets give conflicting specifications about temperature range +1
Answered

Suggested Answer
SC589_EZ-BOARD uses DDR3 with series termination, Why? 0
Suggested Answer

Not Answered
SPORT primary and secondary on EV-SOMCRR-EZLITE +1
Not Answered

Answered
Understanding adi_spdif_Rx_EnableAutoAudioRestart 0
Answered

Answered
Is there a disadvantage to setting SPDIF_RX_CTL.FASTLOCK to 1? 0
Answered

Not Answered
Tx SPORT DMA interruption unaligned with respect to Rx despite same LRCLK and BCLK signals and configs in SHARC-FX ADSP-SC835 +2
Not Answered