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Achieving Stated SHARC Benchmark for Biquad



		

			

									
					    briandb
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jun 28, 2018 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hi,
    
 
    I am using a SHARC 21469 EZ-Kit and want to use a large number of biquads. Having written a standard function in C, I can run 320 biquads running at around 66% CPU (according to the statistical profiler). If I use the SHARC library function biquad_vec(), from filter.h, I can only run 640 biquads, using 73% CPU. I notice when looking at the statistical profiler, that the _biquad_vec() function is being called (at least, that's what it says in the profiler). This implies, as far as I understand from looking at the filter.h file, that the non-SIMD biquad_vec() function is being called  as it makes this distinction based on the SIMD #if defined(__SIMDSHARC__) using #pragma linkage_name _biquad_vec
    
 
    for non-SIMD biquad_vec(). Does that observation sound correct? If it is calling the non-SIMD biquad_vec() library function, how can I get the compiler to link the SIMD version?
    
 
    Second question, related to the SHARC benchmarks here: SHARC Processor Benchmarks | Design Center | Analog Devices 
    
 
    This table states that the ADSP-21469 can execute 1 biquad in 4.43 ns. My current tests are way off this number; how is this execution time achieved? What is the figure (execution time) for the SIMD library function (214xx) per biquad?
    
 
    Thanks,
    
 
    Brian
    
								
    

				
				
		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	
    
		
	
    















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
			                            
                        
                on Jul 6, 2018 9:52 AM
            
            
					
      
	
      

		
		
      
					
      Hello,
      
 
      >>You can refer the FAQ from the below link to enable SIMD operation in your project.
      https://ez.analog.com/docs/DOC-2423
      
 

      >>Regarding SHARC benchmark: As mentioned in the datasheet of ADSP-214xx, the execution time for 1 biquad is around 4.43ns.These benchmarks are captured from the handwritten optimized assembly code (Core algorithm), but not for the Accelerator. Note that, in most of these cases the core takes fewer cycles than the IIR accelerator. The difference between the cycles taken by the core and the accelerator is almost negligible for lower order IIR operations but becomes more significant for higher order IIR operations. This difference increases as the window size are increased.
      
 
      For more details regarding IIR performance, please refer the thread below. This thread contains an example code for finding the number of cycles taken by IIR accelerator for 4 channels, 8 biquad, and 1 window size.
      https://ez.analog.com/message/14841?commentID=14841#comment-14841
      
 
      Best Regards,
      Jithul
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
				
						
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
			                            
                        
                on Jul 6, 2018 9:52 AM
            
            
					
      
	
      

		
		
      
					
      Hello,
      
 
      >>You can refer the FAQ from the below link to enable SIMD operation in your project.
      https://ez.analog.com/docs/DOC-2423
      
 

      >>Regarding SHARC benchmark: As mentioned in the datasheet of ADSP-214xx, the execution time for 1 biquad is around 4.43ns.These benchmarks are captured from the handwritten optimized assembly code (Core algorithm), but not for the Accelerator. Note that, in most of these cases the core takes fewer cycles than the IIR accelerator. The difference between the cycles taken by the core and the accelerator is almost negligible for lower order IIR operations but becomes more significant for higher order IIR operations. This difference increases as the window size are increased.
      
 
      For more details regarding IIR performance, please refer the thread below. This thread contains an example code for finding the number of cycles taken by IIR accelerator for 4 channels, 8 biquad, and 1 window size.
      https://ez.analog.com/message/14841?commentID=14841#comment-14841
      
 
      Best Regards,
      Jithul
      
			
      

		
		
		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
				
						
				
				
		
		
      
			
		
      
	
      

      

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