How should memory ordering and synchronization be handled the SHARC-FX processor on ADSP-21835?

We have a question about memory ordering / synchronization on the ADSP-21835 SHARC-FX processor.

We would like to know whether SHARC-FX processor provides any instruction equivalent to ARM processor barrier instructions such as DMB / DSB / ISB or SHARC+ processor barrier instructions such as SYNC.

Our use case is a single-producer / single-consumer ring buffer.
We want to guarantee the following order:

1. Write data into the ring buffer slot
2. Ensure that write is visible / committed
3. Update the write index afterward

Example:

ring_buffer[write_index] = data;

/* want to insert an operation here that acts as a barrier */

write_index++;
if (write_index >= ring_buffer_max) {
    write_index = 0;
}

Our goal is to avoid publishing the updated write_index before the corresponding data write is safely visible.

Could you please clarify the following?

1. Does the SHARC-FX processor in ADSP-21835 have any architectural barrier instruction equivalent to ARM processor DMB / DSB / ISB or SHARC+ processor SYNC?
2. If not, what is the recommended implementation method for this kind of producer/consumer synchronization?
3. Does the recommendation differ between:
   1. main context <-> ISR on the same SHARC-FX processor
   2. SHARC-FX processor <-> DMA
   3. SHARC-FX processor <-> another core or another bus master
4. For the same-core main/ISR case, is a compiler barrier sufficient?
5. For DMA or other non-coherent shared-memory cases, should cache maintenance (flush/invalidate) and/or non-cacheable memory be used instead?

If there is any relevant documentation, instruction reference, or recommended example for ring buffer / queue synchronization on SHARC-FX, we would greatly appreciate it.

Environment:

• Processor: SHARC-FX (on the ADSP-21835)
• IDE: CrossCore Embedded Studio 3.0.3.0