| S. No. | PHY/Controller | How to configure? | DDR3 | DDR2 | LPDDR | ||||
|---|---|---|---|---|---|---|---|---|---|
| 1 | PHY | DDR3/DDR2/LPDDR modes |
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DDR3 mode should be selected by setting the DMC_PHY_CTL4.DDRMODE bit field to “11”. | ||||
| 2 | PHY | ODT and drive impedance calibration | ODT and drive impedance calibration is supported. Configure the DMC_PADCTL0 and DMC_PADCTL2 registers as per the details in the HRM. Drive impedance calibration is must. Programming ODT is optional, if not used, must make sure that the DMC0_PHY_CTL1.BYODTEN bit is set to bypass the processor ODT settings. | ODT and drive impedance calibration is not supported. No need to program the DMC_PADCTL0 and DMC_PADCTL2 registers. Must make sure that the DMC0_PHY_CTL1.BYODTEN bit is set to bypass the processor ODT settings. | |||||
| 3 | Controller | DDR3/DDR2/LPDDR modes | DDR3 mode should be selected by setting the DMC_CTL.DDR3EN bit. Make sure that the bit DMC_CTL.LPDDR is cleared. | Default is DDR2 mode. Make sure that both the bits DMC_CTL.LPDDR and DMC_CTL.DDR3EN are cleared. | LPDDR mode should be selected by setting the DMC_CTL.LPDDR bit. Make sure that the bit DMC_CTL.DDR3EN is cleared. | ||||
| 4 | Controller | Burst Length | Only burst length of 8 is supported. Configure the DMC_MR0.BLEN field to "00" only. | Both burst length of 4 and 8 is supported. Configure DMC_MR.BLEN field to "10" for burst length of 4 and to "11" for burst length of 8 words. | |||||
| 5 | Controller | CAS latency | CAS latencies of 5 to 14 are supported | CAS latencies of 3 to 6 are supported | Only CAS latency of 3 is supported | ||||
| 6 | Controller | DLLRST bit in DMC_MR(DDR2/LPDDR) or DMC_MR0(DDR3) | This bit must be set while performing the initialization. | Setting of this bit is optional for DDR2. | This bit is reserved in LPDDR mode. | ||||
| 7 | Controller | Write recovery timing | WR values of 5,6,7,8,9,10,12,14,16 are supported. Refer to the DMC_MR0 register description for more details. | WR values of 2,3,4,5,6,7,8 are supported. Refer to the DMC_MR register description for more details. | This bit is reserved in LPDDR mode. | ||||
| 8 | Controller | DMC_MR1(DDR3) or DMC_EMR1 (DDR2) register | This register can be used to configure memory drive impedance, ODT, and additive latency parameters. Refer to the corresponding register descriptions for more details. | This register is not used for LPDDR programming. | |||||
| 9 | Controller | DMC_MR2(DDR3) or DMC_EMR2 (DDR2) or DMC_EMR (LPDDR) register | Configure the write latency field (CWL) to the required value. It can also be used to enable Auto Self Refresh (ASR) and select Self Referesh Temperature (SRT) features in the memory device. For more details on these features refer to the DDR3 memory device data sheets. | This register can be used to configure the Partial Array Self Refresh (PASR) and High Temperature Self-Refresh Rate Enable (SRF) features of DDR2 memory device. For more details on these features, refer to the DDR2 memory device data sheet. | This register can be used to configure the Partial Array Self Refresh (PASR), Temperature compensated self-refresh(TCSR), and drive strengh (DS) features of the memory device. For more details on these features, refer to the LPDDR memory device data sheet. | ||||
