In order to make sure that the single-bit errors are not accumulated over a period of time thus reducing the chances of multi-bit errors, L2CTL provides a memory refresh mechanism for L2 SRAM.
Software can initiate a memory refresh cycle of a 64-bit SRAM entity by writing the address of interest into the refresh address register, L2CTL_RFA. The write triggers an atomic operation. In this operation,the L2CTL performs the following operations:
Applies an ECC algorithm to the two 32-bit words, and
Writes the corrected data back to memory.
For more details, refer ADSP-SC58x/ADSP-2158x HRM.