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Processors and DSP
SHARC Processors
ADSP-SC5xx/ADSP-215xx
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ADSP-SC5xx/ADSP-215xx
Documents
Is there any change in the L1 memory map of SHARC+ Core of ADSP-SC589when compared to SHARC Core in ADSP-214xx family of processors?
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+
ADSP-SC57x/2157x: FAQ
+
ADSP-SC58x: FAQ
+
PMU registers: FAQ
+
SC58x: FAQ
-
SHARC+: FAQ
How many cycles does it take for a branch in SHARC+ ? How can I improve?
Does BTB affect the performance of the SHARC+ core when there is a branch misprediction?
Does hardware loops exist in SHARC+ Core ? Are they different from SHARC Core ?
How to handle Self modifying codes in SHARC+ Core?
In SHARC+ Core, does the external instruction fetch get cached in the Instruction Conflict Cache ?
In SHARC+ Core, for which interrupt does the status push happens automatically?
Is self-nesting of Interrupts allowed in SHARC+ Core?
Is Software Interrupt for Cortex A5 and SHARC core common?
Is the Core interrupt priority programmable in SHARC+ Core as in SHARC Core?
Is the Interrupt Vector table in SHARC+ core same as that in SHARC core?
Is there a scenario which results in a pipeline stall when the SHARC+ core is accessing L1 memory?
How does the DMA (Peripheral and Memory DMA) view SHARC’s L1 memory?
Is there any way that an Interrupt processing can be delayed in SHARC+ Core?
What is the difference between SHARC and SHARC+ Core pipeline?
What is the minimum latency between a Core interrupt and the branch to the IVT?
Are the branch operations impacted by the increase in the number of pipeline stages in SHARC+ Core? If so, how are they mitigated?
Are the CCES Run-time libraries optimized for SHARC+ Core?
Are the registers used to program the core interrupts in SHARC+ same as in SHARC Core?
Are there any new Core interrupts in SHARC+ Core?
Can all the core interrupts be masked in SHARC+ Core?
Is there any change in the L1 memory map of SHARC+ Core of ADSP-SC589when compared to SHARC Core in ADSP-214xx family of processors?
What are the different stages of pipeline in SHARC+ Core ?
What is the number of MAC operations that can be done in parallel in SHARC+ Core?
Where is the default IVT of SHARC+ Core located? Can it be changed?
Which L1 memory alias should the peripherals use to access the SHARC+ L1 Memory?
Will Boot streams generated for SPI master for SHARC+ core only boot on Power on Reset?
+
TMU: FAQ
+
215XX: FAQ
+
ADC Control Module: FAQ
+
ADSP-21584: FAQ
+
ADSP-215xxl: FAQ
+
ADSP-SC573: FAQ
+
ADSP-SC5xx/215xx: FAQ
+
ADSP-SC5xx: FAQ
+
CCES default startup routine: FAQ
+
EMAC: FAQ
+
HADC: FAQ
+
Hardware Counter based Loops: FAQ
+
L1 block: FAQ
+
Preload code customization: FAQ
+
RDEN bit: FAQ
+
RGMII/RMII: FAQ
+
SHARC EE-377: FAQ
+
Sharc SC584: FAQ
+
SMMR using MDMA2: FAQ
+
UCOS: FAQ
+
USBCLKSEL in CGU_CLKOUT: FAQ
+
adsp-sc584: FAQ
+
CDU: FAQ
Custom Error Handler in Booting for SC594
FAQ: ADSP-SC584 SSL Booting via ROM API from the ARM Cortex A5 (core0), SHARC0 and SHARC1
+
IDLE: FAQ
Is it possible to configure the DSP as Master and Host as Slave once SPI slave booting done?
+
Local Oscillator: FAQ
+
MLB channels: FAQ
+
MSI IDMAC: FAQ
+
Program the CBS parameters: FAQ
+
SC57x: FAQ
+
Sign and encrypt a normal bootstream: FAQ
SPI example for ADSP-SC584
+
SPORT with ACM: FAQ
+
SWU: FAQ
Usage of flush_data_buffer api
What is the supported SLCK0 divisor value for ADSP-2156x
Is there any change in the L1 memory map of SHARC+ Core of ADSP-SC589when compared to SHARC Core in ADSP-214xx family of processors?
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Current Revision
25 Jul 2022 7:08 PM
Sara Campbell
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Revision #1
4 Jun 2018 7:40 PM
ADIApproved
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