SHARC+ Core has 11 stages of pipeline .
Four Instruction Fetch Stages (F1,F2,F3,F4)
Decode and DAG[Data Address Generation] (D1 and D2)
Four Data Access Stages (M1,M2,M3,M4)
Execute Stages (E1 and E2)
Fetch1-4: Instruction fetch
DAG: Data Address Generation
Mem1-4: Data access
COF: Jumps, calls, RTS, RTI
Target: COF target
Refer to the ADSP-SC58x Programming Reference Manual for pipeline stage descriptions.