SHARC+ Core has 11 stages of pipeline .
It has
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Four Instruction Fetch Stages (F1,F2,F3,F4)
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Decode and DAG[Data Address Generation] (D1 and D2)
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Four Data Access Stages (M1,M2,M3,M4)
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Execute Stages (E1 and E2)
Fetch1-4: Instruction fetch
DAG: Data Address Generation
Mem1-4: Data access
COF: Jumps, calls, RTS, RTI
Target: COF target
Ex1-2: Compute
Refer to the ADSP-SC58x Programming Reference Manual for pipeline stage descriptions.