Yes. SHARC+ Core is Instruction Set (ISA) and assembly level compatible with SHARC Core. All the existing SHARC Core assembly codes can be used as it is with SHARC+ Core.
It is not guaranteed to be binary level compatible. E.g., in VISA, some instruction may be assembled with uncompressed binary version. Hence the codes has to be reassembled with the new SHARC+ Assembler.
However, due to some stack dependencies, data hazards, and stall conditions, some corner case combinations of code flow will be handled differently from the previous design, which may result in performance degradation if not modified to work well with the new pipeline.
An optimized code for SHARC Core may not be an optimized one for SHARC+ Core. Refer to the Application note EE-375 'Migrating Legacy SHARC to ADSP-SC58x/2158x SHARC+ Processors' for optimizing the hand-written assembly codes for SHARC+ Core.