For all the core interrupts in SHARC+ Core, the processor automatically stacks the arithmetic status (ASTATx, and ASTATy) registers and mode (MODE1) registers in parallel with the servicing of interrupts.The JUMP(CI) and RTI instructions will always automatically pop the status stack.
This behavior in SHARC+ core is in contrast with the SHARC Core where only 3 external interrupts and Core timer interrupt status push happened automatically.