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Can all the core interrupts be masked in SHARC+ Core?
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ADSP-SC5xx/ADSP-215xx requires membership for participation - click to join
Documents
ADSP-SC57x/2157x PCG: What's new?
ADSP-SC57x/2157x Watchdog Timer: What's new?
ADSP-SC58x FMU(Fault Management Unit) Example Code.
ADSP-SC58x SPI Quad example code
ADSP-SC58x/2158x ACM- Example code
ADSP-SC58x/2158x ASRC:Example codes
ADSP-SC58x/2158x Cortex A5 Software Interrupt- Example code
ADSP-SC58x/2158x Counter: Example code
ADSP-SC58x/2158x DAI : What's new?
ADSP-SC58x/2158x interrupt SHARC core from ARM:Example code
ADSP-SC58x/2158x L2 access restriction from MDMA using SMPU - Example code
ADSP-SC58x/2158x Multicore: Example Code
ADSP-SC58x/2158x OTP General Purpose space programming- Example code
ADSP-SC58x/2158x PCG : Example codes
ADSP-SC58x/2158x PKA ECC multiplication - Example code
ADSP-SC58x/2158x PKTE Encryption - Example code
ADSP-SC58x/2158x PKTE Encryption-Hashing - Example code
ADSP-SC58x/2158x PKTE Hashing-Decryption - Example code
ADSP-SC58x/2158x PWM: What's new?
ADSP-SC58x/2158x SPDIF-RX feature list: What's new?
ADSP-SC58x/2158x SPDIF: Example code
ADSP-SC58x/2158x SPI - Example Code
ADSP-SC58x/2158x SPI XIP - Example code
ADSP-SC58x/2158x TRNG - Example code
ADSP-SC58x/2158x UART autobaud - Code Example
ADSP-SC58x/2158x Watchdog Timer:Example code
ADSP-SC58x/ADSP-215xx SHARC+ Core Timer with Interrupt Example Code
ADSP-SC5xx/ADSP-215xx - Sweep Test
Are the branch operations impacted by the increase in the number of pipeline stages in SHARC+ Core? If so, how are they mitigated?
Are the CCES Run-time libraries optimized for SHARC+ Core?
Are the registers used to program the core interrupts in SHARC+ same as in SHARC Core?
Are there any new Core interrupts in SHARC+ Core?
Can all the core interrupts be masked in SHARC+ Core?
Can ARM Cortex A5 access SHARC core internal memory space in ADSP-SC58x?
Can FIR accelerator access both on chip and off chip memories on ADSP-SC58x/ADSP-2158x processor?
Can I access the PMU registers as co-processor register?
Can I connect DDR3 memory device on one DMC and DDR2 memory device on another DMC on ADSP-SC58x/ADSP-2158x?
Can I use the MLB Clock on SC58x to clock an external system?
Can IIR accelerator access both on chip and off chip memories on ADSP-SC58x/ADSP-2158x?
Can Performance Monitor Unit be used to calculate cycle counts for SHARC core?
Can the CRC engine on ADSP-SC58x/ADSP-2158x be used to calculate 16 bit CRC ?
Can the existing SHARC assembly codes be re-used as it is with SHARC+ Core?
Can we single-step over the IDLE instruction?
Code Example: Controller Area Network (CAN) for ADSP-SC573
Do both the SHARC+ Cores in ADSP-SC58x/ADSP-215xx share the same L1 Memory?
Does BTB affect the performance of the SHARC+ core when there is a branch misprediction?
Does hardware loops exist in SHARC+ Core ? Are they different from SHARC Core ?
Does MDMA support descriptor based DMAs on ADSP-SC58x/ADSP-2158x?
Does the user have option to decide between F1 Active mode and E2 Active mode in Hardware Counter based Loops?
Does USBCLKSEL in CGU_CLKOUT register have any effect on USB operation?
Effect of bus disabling (RDEN bit) on RTC functionality
EMAC does not come out of software reset. What could be the issue?
FAQ - Preload code customization for 215XX processors
FAQ: How to access SMMR using MDMA2- Example code
FAQ: How to synchronize multicores with TRU or Interrupt?
FAQ: Looking for a USB peripheral mode code example for Sharc SC584
FAQ: Memory gaps inserted between different sections in L1 block
FAQ: Preload code customization
FAQ: Questions related to stack size in UCOS
FAQ: SPORTs Synchronization in SHARC EE-377 Talkthrough Example
FAQ: What is Multiprocessor Offset in ADSPSC58x/ADSP-215xx processors??
FAQs on ADSP-SC5xx OTP
FIRA/IIRA Performance on ADSP-SC58x/2158x and ADSP-SC57x/2157x Processors
HADC maximum available bandwidth
Highlights of MSI on ADSP-SC58x
How Cache initialization can be bypassed from the CCES default startup routine?
How can I boot an ADSP-21584 based SHARC application on an ADSP-SC584 part?
How can I boot an ADSP-21584 based SHARC application?
How can I choose between RGMII/RMII interfaces in EMAC?
How can I estimate the sample rate of the SPORT frame sync input on ADSP-SC5xx/ADSP-215xx processors?
How can I run the core clock at maximum of 450MHz and also source a 125MHz at the CLK07 for the EMAC TXCLK?
How can I validate the DDR interface on my newely designed board based on ADSP-SC58x/ADSP-2158x processors?
How can the high speed FFTA DMA engine on ADSP-SC58x/ADSP-2158x be used in MDMA mode?
How DMC/DDR controller in ADSP-SC58x/ADSP-2158x different than DDR2 controller on ADSP-2146x ?
How does the ACM module work?
How does the DMA (Peripheral and Memory DMA) view SHARC’s L1 memory?
How does the ECC error protection on L2 memory system works on ADSP-SC58x/ADSP-2158x processors?
How does the memory refresh operation in L2CTL memory system works on ADSP-SC58x/ADSP-2158x processors?
How FFT accelerator (FFTA) on ADSP-SC58x/ADSP-2158x is different as compared to ADSP-214xx processors / What are the major features of FFTA on ADSP-SC58x/ADSP-2158x ?
How FFT accelertor on ADSP-SC58x/ADSP-2158x can be programmed?
How FIR accelerator on ADSP-SC58x/ADSP-2158x is different than the FIR accelerator on ADSP-214xx?
How IIR accelerator on ADSP-SC58x/ADSP-2158x is different than the FIR accelerator on ADSP-214xx?
How is GP Timer in SC57x/2157x different from that of SC58x?
How is SWU on SC58x different from that on BF60x processor?
How is the ACM on SC58x different from that on BF60x processor?
How is the MLB interface on SC58x different from previous SHARC processors?
How is the SPI peripheral different from the older SHARC processors?
How many CRC blocks available on ADSP-SC58x/ADSP-2158x processor ?
How many cycles does it take for a branch in SHARC+ ? How can I improve?
How many DMC controllers are present in ADSP-SC58x/ADSP-2158x processors?
How many instances of EMAC are present in SC58x? How are they different?
How many MDMA streams are supported by ADSP-SC58x/ADSP-2158x processors and how much bandwidth they support?
How the FIR and IIR accelerators in ADSP-SC57x/2157x processors are different than in ADSP-SC58x/2158x processors
How to configure GIC of edge triggered interrupt sources?
How to configure MSI IDMAC for Dual Buffer Descriptor Ring mode operation
How to enable only L1 cache and not L2 cache OR vice-versa?
How to extend number of channels in HADC
How to handle Self modifying codes in SHARC+ Core?
How to select PSIZE and MSIZE fields of the MDMA configuration register on ADSP-SC58x/ADSP-2158x ?
How to sign and encrypt a normal bootstream for Secure Boot?
I have configured my MDMA on ADSP-SC58x correctly, but still the MDMA transfer doesn't work as expected. Am I missing something?
I installed the IIR DMA interrupt handler on ADSP-SC58x, but still the interrupt doesn't occur, what I may be missing?
I want to use the Credit Based Shaping feature to allot a particular bandwidth to Channel 2. How do I program the CBS parameters to achieve the same?
In ADSP-SC58x, can the ARM core access the SHARC+ Core's L1 Memory?
In SHARC+ Core, does the external instruction fetch get cached in the Instruction Conflict Cache ?
In SHARC+ Core, for which interrupt does the status push happens automatically?
Is it possible to change the default boot mode peripheral instances?
Is it possible to run a DDR2 device at DCLK=400 MHz, CCLK=450 MHz, SYSCLK=225Mz on ADSP-SC58x/ADSP-2158x processors?
Is it possible to run all the accelerators FIR/IIR/FFT in ADSP-SC58x/ADSP-2158x simultaneously?
Is Secure booting supported in Open part in ADSP-SC58x?
Is self-nesting of Interrupts allowed in SHARC+ Core?
Is Software Interrupt for Cortex A5 and SHARC core common?
Is the Core interrupt priority programmable in SHARC+ Core as in SHARC Core?
Is the Interrupt Vector table in SHARC+ core same as that in SHARC core?
Is there a restriction in use of stall count mode and burst length increment in SWU?
Is there a restriction on the number of MLB channels that I can use concurrently?
Is there a scenario which results in a pipeline stall when the SHARC+ core is accessing L1 memory?
Is there a way to slow down the compute engine of the FFTA on ADSP-SC58x/ADSP-2158x processor?
Is there any change in the L1 memory map of SHARC+ Core of ADSP-SC589when compared to SHARC Core in ADSP-214xx family of processors?
Is there any L2 cache in ADSP-SC58x?
Is there any restriction on the DMA programming for MLB channels?
Is there any restriction on the types of memories supported by MDMA on ADSP-SC58x/ADSP-2158x?
Is there any way that an Interrupt processing can be delayed in SHARC+ Core?
Is there anything equivalent to External Port DMA (EPDMA) on ADSP-214xx processors available on ADSP-SC58x/ADSP-2158x processors?
Is VFP and Neon available in ADSP-SC58x?
LWIP on SC584 EzKit
SC57x watchdog timer
Secure Slave boot modes fails to boot even after programming the correct Public and Private key in the OTP space in ADSP-SC58x. What else is missing?
TMU: Monitor thermal state of processor
Using 10/100 emac with LWIP on SC58x
What all Boot modes are supported in ADSP-SC58x?
What are the activities that can take place when core is executing IDLE instruction ?
What are the different stages of pipeline in SHARC+ Core ?
What are the important features of the L2 memory system on ADSP-SC58x/ADSP-2158x processors?
What are the major changes in the programming model of the FIR accelerator on ADSP-SC58x/ADSP-2158x as compared to ADSP-214xx processors?
What are the major changes in the programming model of the IIR accelerator on ADSP-SC58x/ADSP-2158x as compared to ADSP-214xx processors?
What are the major differences in between the programming model of DDR3, DDR2, and LPDDR modes in the DMC controller of ADSP-SC58x/ADSP-2158x?
What are the major features of the CRC engine on ADSP-SC58x/ADSP-2158x processors?
What are the programming guidelines to use SPORT with ACM?
What DDR3/DDR2/LPDDR device sizes are supported by the DMC controller on ADSP-SC58x/ADSP-2158x?
What is CDU and how is it linked with CGU?
What is maximum speed of operation supported by Link Port in ADSP-SC58x?
What is Oscillator Watchdog?
What is the difference between SHARC and SHARC+ Core pipeline?
What is the maximum DMA throughput supported by L2CTL memory system on ADSP-SC58x/ADSP-2158x processors?
What is the maximum processing speed supported by Cortex-A5 in ADSP-SC58x?
What is the maximum speed supported by the MLB interface on SC58x?
What is the minimum DCLK frequency supported for various DDR modes on ADSP-SC58x/ADSP-2158x?
What is the minimum latency between a Core interrupt and the branch to the IVT?
What is the number of MAC operations that can be done in parallel in SHARC+ Core?
What is the size if L1 cache supported by Cortex A5 in ADSP-SC58x?
What is use of Local Oscillator in TMU
What should I do to SYS_CLKIN1 on SC58x, if I need only one CLKIN in my system
what's new in the SPI peripheral of SC58x processor?
When would Bandwidth overflow / underflow event be generated with scaling feature enabled of SWU?
Where is the default IVT of SHARC+ Core located? Can it be changed?
Which L1 memory alias should the peripherals use to access the SHARC+ L1 Memory?
Will Boot streams generated for SPI master for SHARC+ core only boot on Power on Reset?
Will the application mapped for XIP (Continuous read mode) from the SPI Flash boot on second System reset?
Can all the core interrupts be masked in SHARC+ Core?
No , RESET and Emulation Interrupt are non-mask able interrupt . This is the same in the SHARC Core.
interrupt
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