No. Both SHARC+ cores in ADSP-SC58x/ADSP-2158x has its own L1 Memory and its size is 5M bits each. The address map is the same for L1 Memory of both the SHARC Cores.
For a system to differentiate between the two SHARC+ cores, a new memory alias is introduced for L1 memory of both the SHARC Cores. This is called the System space (Multiprocessor Space) of L1 Memory.
Hence the entire L1 memory address space has 2 views :