Yes, The ARM can access the L1 memory of both the SHARC+ cores in ADSP-SC58x. Both data access and code execution is supported. ARM core can access SHARC+ L1 memory through SHARCs L1 memory multiprocessor addresses alias.
I solved my ARM to SHARC write-problem by changing the ARM MMU default settings in the file apt-sc589.c file, .. from Read Only (-RO-) to -RW-. This file is located in the CorsCore ARM-installation parth…
I am able to read the data of SHARC L1 memory region from ARM core, but not able to write. Can you please share the sample project of the same, it will be helpful.
I solved my ARM to SHARC write-problem by changing the ARM MMU default settings in the file apt-sc589.c file, .. from Read Only (-RO-) to -RW-. This file is located in the CorsCore ARM-installation parth.
I Copied this file to the project files, changed the setting for the given SHARC-1 and -2 L1-memmory regions, compiled the project and now the ARM - SHARC memory access - in uinfied memory space - worked with no problems.
No ,there is no protection that has to be unlocked as ARM core is the secure master.
Is the SHARC core out of reset at the time when ARM tries to access its L1 space?
Can you provide me a simple project which replicates the issue ?
I tried to write to SHARC1 L1 memory location, from the ARM core, using the unified address mem. space.
The addres semes to be correct, but I get a
"No dispatched handler available for the specified interrupt code."
Is the some kind of protection, that has to be unlocked?
I have lock on the SMPU Registers - but I think this does not concern L1 memory.
Have any body a good idea?