In the SHARC Core of ADSP-214xx processors, all the external instruction fetch used to get cached in the Instruction Conflict Cache in addition to its main function of caching the instruction when there is a PMD bus conflict. Now this feature is depreciated in SHARC+ Core and only the PMD bus conflict instructions are cached in Instruction Conflict Cache.
The introduction of a separate L1 Cache Controller in SHARC+ core has taken care of caching any external instruction fetches.