The ADSP-SC58x/2158x processors have new SPDIF receiver design. The features are:
1. It supports sampling rates from 24KHZ to 96KHZ
2. It can detect Audio word length from channel status bits as specified by IEC 60958-3
3. It can detect compression type by using burst info as specified by IEC 61937-2
4. It can detect whether compression type is DTS or AC3.
5. It doesn't support interrupt for CRC error and parity error and emphasized audio( These are supported in ADSP-214xx).
6.The SCDF mode which was supported in ADSP-214xx is not available in new design
Yes, your understanding is correct. ADSP-SC58x processor requires SPDIF signal (Biphase stream) to be of 0 to 3.3v signal levels. We need LVDS transceivers to convert Standard coaxial line voltage levels (500mv) to 3.3V of the processor. It's similar to how we use UART transceivers for UART to convert 3.3v to physical line standards.
We are planning to use the ADSP-SC587 chip for one of our new projects which includes the SPDIF input and output connection.
We have one doubt regarding the SPDIF driving circuit given in the ADSP-SC589 EZ-Board schematics. Why the SPDIF coax input is connected to an LVDS receiver ? Does it is for changing the standard SPDIF voltage level of 0.2V - 0.6V to a 3.3V level of ADSP ? or is there any other reason for that ? The SPDIF itself is unbalanced by standard and why we the circuit is designed in such a way that it is treated just like a differential input of an LVDS line receiver [ correct me if I am wrong ] ? Please do share more information regarding the SPDIF section..