Yes. The ARM Cortex-A5 processor can access any memory space on the chip including the SHARC L1 memory, the system L2 SRAM and all external memory spaces. The Cortex-A5 processor has access to all peripherals as well.
Hi Harshit, Thanks for the information.
It is actually my project requirement to build with the already in place make file build system.
I understand that you are using the same tool chain which comes with CCES installation to build the project.
May I know the reason why are you not generating the project using CCES. If you will do that, it takes care of all the start-up routine such as stack initialization, cache invalidation, MMU table initialization etc. before reaching to the main().
After this if you want to change the VBAR to your SRAM address then that is possible by executing the following code:
“ MRC P15, 0, R4, C12, C0, 0 /* Set the vector base address to the vector table */
LDR R4, =vectors_start
MCR P15, 0, R4, C12, C0, 0”
The VBAR bit definition is shown below:
Bits[31:5] holds the base address of the low exception vectors.
Bits[4:0] of an exception vector is the exception offset/reserved and holds the entry for the Reset, Undefined Exception, Prefetch Abort, Data Abort, IRQ, FIQ etc.
Same has been explained in the below link:
Hope this helps.
I would also request you to next time post a separate Forum thread in case you have any new queries which is not related to this FAQ page. This will help other viewers on this community to track the issues properly and use it as a reference.
Thank you so much for the invaluable information, i have another question.actuallay i am not creating project in the CCES, i am using the CCES to debug my application only.
tool chain i am using for building my application is the same installed with CCES (crosscore arm bare-metal tool chain).
When I set the VBAR register, it sets the vector start address but the lower 8 bits of the VBAR are not set.
(The lower 4 Bits of VBAR register are mentioned to be reserved on ARM info center.)
Don't know how the CCES project sets the complete address of the vector table.
And sorry if my question is too naive
The address is 0x0 is a Boot ROM space and cannot be accessed by the user.
Once you create a project in the CCES, it has a default startup routine which configures the Vector table to local SRAM space.
This can be also checked by reading the VBAR register or you can search for the vectors_start in the disassembly.
Please let me know if you have any further queires.
Yes that was very helpful. Actually I need to configure Interrupts and for that I need my Interrupt vector table to be placed at 0x00000000 or 0xFFFF0000 for CortexA5 to access it.
Does it mean that 0xFFFF0000 cannot be used and if so, can you please direct me to some example in which IVT is configured. Because if I configure the IVT to be stored at address 0x00000000 in the linkerscript, I get an error during loading.