No. The interrupt in Cortex A5 and SHARC core is handled via GIC and SEC respectively.
GIC has a dedicated 8 interrupts (GIC Interrupt ID 0-7) as Software Interrupt. This can be used to generate an interrupt in Cortex A5 core only and not SHARC cores.
However triggering of these software interrupts can be done from any cores.
My question is regarding the triggering the interrupt in SHARC core itself. Using the adi_int API's we can trigger the interrupt in ARM core. For example
adi_int_InstallHandler(0, Software_Int0, 0, 1);
This will trigger the Software_Int0() interrupt. Are there ant API's like this, that will trigger the interrupt in SHARC cores. Why we need to use the *pREG_SEC0_RAISE to trigger the interrupt in SHRAC core itself.
The example code is captured in below forum link:
Can you please share an example of handling interrupts for SHARC and ARM core?