By default when the project is created in the CCES for Cortex A5 core in ADSP-SC58x processor, the cache for both L1 and L2 space is enabled. If the user want to have only one enabled/disabled in the application this can be done by defining the following in the application:
/* To disable Cache */
uint32_t adi_cache_gEnable = 0;
/*To enable only L1 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L1;
/*To enable only L2 cache cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L2;
/*To enable both L1 and L2 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_ALL;
With your inputs I am able to enable the L1 cache on the SHARC core. How to change the size? Is through the system.svc file or by setting the register value we can change it?
I have some doubts regarding the system L2 memory. Here you are telling about the ARM L2 cache can be enabled/disabled from ARM core. What about the system L2 memory(256 KB SRAM) which is shared to all the cores. Cant we configure this as cache from SHARC core project? If we can how to do it.
Let me know if I am wrong understanding the L2 memory .
1. You should be able to change the size of SHARC L1 cache in Cache configuration wizard in system.svc . In addition to enabling the Cache and setting the size, this also changes the L1 memory size ldf to accommodate the change in the cache size. Any change in the cache size in system.svc should be reflected in the REG_SHL1C0_CFG register. Read this register to confirm that the change took place. If not (For ADSP-SC589 0.1 silicon revision, changes in system.svc will not affect the REG_SHL1C0_CFG register), directly write to the REG_SHL1C0_CFG register appropriate bits to change the cache size.
2. Yes , Only ARM can configure the L2 Cache controller. But the SHARC core accesses can be cached in L2 cache by programming the range register pair
So to use the L2 cache for SHARC core external accesses
a. Make sure that the L2 cache controller is enabled
b. Program the REG_CMMR0_L2CC_START and REG_CMMR0_L2CC_END registers with appropriate memory addess from the SHARC+ core. SHARC+ core access to any address in this range will be cached in L2 cache
c. If the L2 Cache is to be disabled for SHARC+ accesses, write ZERO to the range register pair.
Hope this helps
Hi Harshit and Mahesh,
Thanks for your feedback. In SHARC+ core project, when I am including the #include <runtime/cache/adi_cache.h> its not able to locate the header file. Do I need to add any libraries into the project. When I am adding "sys/cache.h", I am not finding the mcros related to the cache enabling.
Can you please share a small snippet of the code for SHARC project, which will enable the cache (I, D and P). ?
What I am trying to do is evaluating the FFT api's avaialble in CCES, when I am putting the data in different memory location. I want to enable the cache and see how the results are coming.
Any help on this will be of great helpful.
Thanks for your response,
By default, is cache enabled for SHARC cores, or we need to manually enable it.?
I also want to enable the cache of the SDARM when we are accessing the data from it, how to do that? Can we enable the cache for the SDRAM to L1? How we can configure the cache for different page files?
You need to include above lines in your project and then uncomment accordingly to your requirement:
For example, if you want to enable only L1 cache but not L2, then add below code snippet in your main.c file of the project.
//uint32_t adi_cache_gEnable = 0;
//uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L2;
//uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_ALL;
Please let me know if you have any further queries.