By default when the project is created in the CCES for Cortex A5 core in ADSP-SC58x processor, the cache for both L1 and L2 space is enabled. If the user want to have only one enabled/disabled in the application this can be done by defining the following in the application:
/* To disable Cache */
uint32_t adi_cache_gEnable = 0;
/*To enable only L1 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L1;
/*To enable only L2 cache cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L2;
/*To enable both L1 and L2 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_ALL;
How to enable/disable the particular cache for the SHARC core in ADSP-SC58x processor. Can you please share the example source code of the same.?
You need to include above lines in your project and then uncomment accordingly to your requirement:
For example, if you want to enable only L1 cache but not L2, then add below code snippet in your main.c file of the project.
//uint32_t adi_cache_gEnable = 0;
//uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L2;
//uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_ALL;
Please let me know if you have any further queries.
Thanks for your response,
By default, is cache enabled for SHARC cores, or we need to manually enable it.?
I also want to enable the cache of the SDARM when we are accessing the data from it, how to do that? Can we enable the cache for the SDRAM to L1? How we can configure the cache for different page files?
I am also working on cache issues, with CCES 2.4.0 and i've stumbled upon this thread. I wanted to ask you, what do you mean by this symbol, "adi_cache_gEnable"? I couldn't find its definition. Is it used to configure any register directly?
Thanks a lot,