By default when the project is created in the CCES for Cortex A5 core in ADSP-SC58x processor, the cache for both L1 and L2 space is enabled. If the user want to have only one enabled/disabled in the application this can be done by defining the following in the application:
/* To disable Cache */
uint32_t adi_cache_gEnable = 0;
/*To enable only L1 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L1;
/*To enable only L2 cache cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L2;
/*To enable both L1 and L2 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_ALL;
How to enable/disable the particular cache for the SHARC core in ADSP-SC58x processor. Can you please share the example source code of the same.?
SHARC+ L1 cache :
Refer to "CCES Help" for information on the library codes available to support SHARC+ L1 Cache. Cache configuration can be set in the generated LDFs via the Cache Configuration tab in the Startup Code/LDF wizard in system.svc file.
NOTE : Due to some Cache anomalies in ADSP-SC58x Rev 0.0/0.1 , by default, the Cache is NOT enabled as part of the start-up code even though the Cache seems to be enabled in the Cache Configuration tab in the Startup Code/LDF wizard.
Hence users are requested to enable the cache in their application by using the below code
//Code to Enable all the 3 caches with size 16KB
*pREG_SHL1C0_CFG = ((1 << BITP_SHL1C_CFG_ICAEN) | (1 << BITP_SHL1C_CFG_ICAINV)
| (1 << BITP_SHL1C_CFG_DMCAEN) | (1 << BITP_SHL1C_CFG_DMCAINV)
| (1 << BITP_SHL1C_CFG_PMCAEN) | (1 << BITP_SHL1C_CFG_PMCAWB));
adi_rtl_wait_for_cache_latency(); // 11 cycle latency
Refer to the SHARC+ Programmer’s Reference Manual: http://www.analog.com/media/en/dsp-documentation/processor-manuals/SC58x-2158x-prm.pdf
Chapter 8: L1 Cache Controller (Pg. No 279) to setup cache for different size.
ARM L2 Cache Sharing Address Range Registers:
ARM L2 cache can only be enabled /disabled from the ARM core. SHARC core access through the ARM L2 cache is done using the L2 cache address register pair (REG_CMMR0_L2CC_START and REG_CMMR0_L2CC_END)
In order to achieve data coherency between the ARM and the SHARC+ core at the L2 cache level, the processor provides a connection between the SHARC and the L2 cache of the ARM.
The SHARC core can access system memory directly or via ARM L2 cache. When the L2 cache address register pair is cleared, the SHARC+ data port read data directly from system memories (L2/L3) through the system fabric. However when the L2 cache address register pair have L2/L3 addresses configured the SHARC+ data port reads data via A5 L2 cache from the system memories.
Hi Harshit and Mahesh,
Thanks for your feedback. In SHARC+ core project, when I am including the #include <runtime/cache/adi_cache.h> its not able to locate the header file. Do I need to add any libraries into the project. When I am adding "sys/cache.h", I am not finding the mcros related to the cache enabling.
Can you please share a small snippet of the code for SHARC project, which will enable the cache (I, D and P). ?
What I am trying to do is evaluating the FFT api's avaialble in CCES, when I am putting the data in different memory location. I want to enable the cache and see how the results are coming.
Any help on this will be of great helpful.
1. You should be able to change the size of SHARC L1 cache in Cache configuration wizard in system.svc . In addition to enabling the Cache and setting the size, this also changes the L1 memory size ldf to accommodate the change in the cache size. Any change in the cache size in system.svc should be reflected in the REG_SHL1C0_CFG register. Read this register to confirm that the change took place. If not (For ADSP-SC589 0.1 silicon revision, changes in system.svc will not affect the REG_SHL1C0_CFG register), directly write to the REG_SHL1C0_CFG register appropriate bits to change the cache size.
2. Yes , Only ARM can configure the L2 Cache controller. But the SHARC core accesses can be cached in L2 cache by programming the range register pair
So to use the L2 cache for SHARC core external accesses
a. Make sure that the L2 cache controller is enabled
b. Program the REG_CMMR0_L2CC_START and REG_CMMR0_L2CC_END registers with appropriate memory addess from the SHARC+ core. SHARC+ core access to any address in this range will be cached in L2 cache
c. If the L2 Cache is to be disabled for SHARC+ accesses, write ZERO to the range register pair.
Hope this helps
With your inputs I am able to enable the L1 cache on the SHARC core. How to change the size? Is through the system.svc file or by setting the register value we can change it?
I have some doubts regarding the system L2 memory. Here you are telling about the ARM L2 cache can be enabled/disabled from ARM core. What about the system L2 memory(256 KB SRAM) which is shared to all the cores. Cant we configure this as cache from SHARC core project? If we can how to do it.
Let me know if I am wrong understanding the L2 memory .
I am able to configure the L1 cache and its size. Now I am want to configure the L2 cache. I am enabling the L2 cache as suggested by Harshit.Gaharwar in the above comment. I want to make sure whether it is enable or not. How to make sure whether L2 cache controller is enabled or not?
Is it not necessary to program the address range for L1 cache.? What are the locking range register.?
If you have small snippet of the code please share.