By default when the project is created in the CCES for Cortex A5 core in ADSP-SC58x processor, the cache for both L1 and L2 space is enabled. If the user want to have only one enabled/disabled in the application this can be done by defining the following in the application:
/* To disable Cache */
uint32_t adi_cache_gEnable = 0;
/*To enable only L1 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L1;
/*To enable only L2 cache cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L2;
/*To enable both L1 and L2 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_ALL;
I am also working on cache issues, with CCES 2.4.0 and i've stumbled upon this thread. I wanted to ask you, what do you mean by this symbol, "adi_cache_gEnable"? I couldn't find its definition. Is it used to configure any register directly?
Thanks a lot,
Do you want to use L2 cache with SHARC+ core?
If this is the case, then you have to follow these two steps
2. From the SHARC core , program the REG_CMMR0_L2CC_START and REG_CMMR0_L2CC_END registers with appropriate memory address for which you need to the L2 cache enabled for SHARC+ core
Thanks for your support, we are able to enable the L1 cache and make use of it.
We want to make use of the L2 cache. How to enable the L2 cache, and how to verify whether the L2 cache is enable or disabled?
How to configure the range of the L2 cache.?
Any information on this will be of great helpful.
I am able to configure the L1 cache and its size. Now I am want to configure the L2 cache. I am enabling the L2 cache as suggested by Harshit.Gaharwar in the above comment. I want to make sure whether it is enable or not. How to make sure whether L2 cache controller is enabled or not?
Is it not necessary to program the address range for L1 cache.? What are the locking range register.?
If you have small snippet of the code please share.
I can comment on the L1 Cache configuration
When the L1 cache is enabled, all the external memory access (L2 memory and DDR memory) will be cached. There is no need to program the address range for L1 cache .
Having said that, SHARC L1 Cache do have range register pairs which serves various special purposes. I would recommend you to go through the SHARC+ ADSP-SC58x Programming reference manual http://www.analog.com/media/en/dsp-documentation/processor-manuals/SC58x-2158x-prm.pdf L1 cache controller chapter for information on the various Range based register functionality.
If you have any queries on the L1 cache, please start a new thread and I would be happy to answer all the questions.