By default when the project is created in the CCES for Cortex A5 core in ADSP-SC58x processor, the cache for both L1 and L2 space is enabled. If the user want to have only one enabled/disabled in the application this can be done by defining the following in the application:
#include <runtime/cache/adi_cache.h>
/* To disable Cache */
uint32_t adi_cache_gEnable = 0;
/*To enable only L1 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L1;
/*To enable only L2 cache cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_L2;
/*To enable both L1 and L2 cache */
uint32_t adi_cache_gEnable = ADI_CACHE_ENABLE_ALL;