Before starting application development on a newly designed board with ADSP-SC58x/ADSP-2158x processors along with DDR3/DDR2/LPDDR memory interface, it is very important to make sure that there are no basic issues with the DMC(Dynamic Memory Controller) interface itself. The following steps can be followed to validate the DMC interface on ADSP-SC58x/ADSP-2158x processors:
EE-387 provides the files “DMCInit_Debug.c/h” which contain function “Memory_Sweep_Test()” to test both the core and DMA (MDMA) accesses to the DDR device for various data patterns and memory widths (8/16/32/64 bits). It also contains the function to print the programmed values of the DMC registers which can be used to cross verify whether the programmed values are indeed correct. For more details, refer “Validating the DMC Interface “section of EE-387.
This document is very helpful.
However, problems starts with sc584 when one needs:
- CLKIN = 25 MHz
- ARM CLK = 450 MHz (max allowed)
- DDR2 = 400 MHz (max supported)
- RGMII/GbitE CLK = 125 MHz
- Linkport = 150MHz.
Is it possible to have those maximal frequencies set with two CGUs?