In addition to traditionally supported long word, normal word, extended precision word and short word addressing aliases, the ADSPSC5xx/ADSP-215xx processors support byte addressing for the data and instruction accesses.
Any buffer/array defined in SHARC+ core will by default map to SHARC’s internal byte address space.
Below image shows the SHARC+ core’s private address space.
SHARC+ L1 memory can also be accessed by another SHARC core/ARM core or other peripheral DMA/Memory-to-memory DMA through multiprocessor byte address space. The table below shows SHARC+ L1 memory in multiprocessor space.
The L1 Private Memory space of SHARC+ can be accessed directly by itself without adding any offset. In order to access these internal memories from another SHARC core/ARM core or other peripheral DMA/Memory-to-memory DMA an offset (multiprocessor offset) is added which is shown below:
SHARC’s L1 memory can thus be accessed using different slave ports on adding the above offsets considering the system optimization technique appropriate for the application.
For example, to access address 0x240000 of SHARC1 using slave port 1through multiprocessor space, it can be accessed as 0x28240000 (->0x28000000 | 0x240000 = 0x28240000). Further , to access address 0x240000 of SHARC2 using slave port 1through multiprocessor space, it can be accessed as 0x28A40000 (-> 0x28800000 | 0x240000 = 0x28A40000).
Please find an example code (Multiprocessor_offset) attached for the reference. The details are given below for better understanding.
Multiprocessor_offset_Core0: The ARM core writes data to the L1 memory (block2) of SHARC1 in Multiprocessor space via Slave port1. This data read by the ARM again and writes to the L1 memory (block2) of SHARC2 in Multiprocessor space via Slave Port1.
NOTE: The ARM MMU (Memory Management Unit) is configured to access the SHARC's L1 multiprocessor space as Read only. Please see the apt-sc589.c file which shows the memory attributes for all the memory sections. The file can be copied from below path:
...\Analog Devices\CrossCore Embedded Studio 2.3.0\ARM\arm-none-eabi\arm-none-eabi\lib\src\cortex-a5\crt\apt-sc589.c
For instance, the L1 memory of SHARC0 in MP space via Slave1 port is configured in apt-sc589.c as below.
/* L1 memory of SHARC0 in MP space via Slave1 port */ { 0x28240000u, 0x2826FFFFu, ADI_MMU_RO_UNCACHED }, /* 192KB SHARC0 L1B0 */
{ 0x282C0000u, 0x282EFFFFu, ADI_MMU_RO_UNCACHED }, /* 192KB SHARC0 L1B1 */
{ 0x28300000u, 0x2831FFFFu, ADI_MMU_RO_UNCACHED }, /* 128KB SHARC0 L1B2 */
{ 0x28380000u, 0x2839FFFFu, ADI_MMU_RO_UNCACHED }, /* 128KB SHARC0 L1B3 */
In case you want to write into the multiprocessor space from ARM core then the attributes can be changed by copying this file to your local project and the making the change as RW instead of RO as shown below:
/* L1 memory of SHARC0 in MP space via Slave1 port */ { 0x28240000u, 0x2826FFFFu, ADI_MMU_RW_UNCACHED }, /* 192KB SHARC0 L1B0 */
{ 0x282C0000u, 0x282EFFFFu, ADI_MMU_RW_UNCACHED }, /* 192KB SHARC0 L1B1 */
{ 0x28300000u, 0x2831FFFFu, ADI_MMU_RW_UNCACHED }, /* 128KB SHARC0 L1B2 */
{ 0x28380000u, 0x2839FFFFu, ADI_MMU_RW_UNCACHED }, /* 128KB SHARC0 L1B3 */
Multiprocessor_offset_Core1: The SHARC1 core does MDMA from the source buffer declared in its L1 block 0 to destination buffer declared in the L3 (DDR memory). Since SHARC1 does DMA, its own memory should be accessed with corresponding multiprocessor memory offset.
Multiprocessor_offset_Core2: The SHARC2 core writes data to its L1 memory block1 and L1 memory block1 of SHARC2. See the comment embedded in the code for better understanding.